Semiconductor device having a miniature junction area and proces

Details Semiconductor device having a miniature junction area and proces Semiconductor device having a miniature junction area and proces

1977-03-02

1978-02-14

James, Andrew J.

Metal treatment

Stock

Ferrous

357 40, 357 49, 357 54, 357 65, 357 68, 148175, 148187, 148189, 29625, H01L 2904, H01L 2702, H01L 2934, H01L 2348

Patent

active

040743047

ABSTRACT:
In a method for fabricating a semiconductor device, a polycrystalline film deposited on a main surface of a substrate is subjected to selective oxidation to form polycrystalline silicon electrode wiring paths separated by silicon oxide. An impurity of a conductivity type opposite to that of the substrate is introduced through at least one of the wiring paths into the substrate. Also disclosed is a novel semiconductor device fabricated according to this process which has a reduced junction area and a shortened junction-to-electrode distance.

REFERENCES:
patent: 3456335 (1969-07-01), Hennings et al.
patent: 3664896 (1972-05-01), Duncan
patent: 3717514 (1973-02-01), Burgess
patent: 3761327 (1973-09-01), Harlow
patent: 3791024 (1974-02-01), Boleky
patent: 3796613 (1974-03-01), Magdo et al.
patent: 3806361 (1974-04-01), Lehner
patent: 3847687 (1974-11-01), Davidsohn
patent: 3947299 (1976-03-01), Weijland
Quadratpilze aus Polysilicon, No. 3, vol. 15, Jan. 1974.

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