Semiconductor device having a mesa structure for surface voltage

Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – Mesa structure

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257170, 257171, 257452, 257466, 257586, 257600, 257618, H01L 2906, H01L 2974

Patent

active

057738742

ABSTRACT:
A semiconductor device comprises a monocrystalline silicon wafer having a major surface lying in the <100> crystal plane. Disposed on the surface is a mesa having a generally square cross-section with generally rounded corners. The mesa has four main side walls each having a slope of around 45 degrees with respect to the base plane of the mesa, and the horizontal edges of the main side walls are disposed at an angle of at least around 12 degrees to the <110> directions on the wafer surface. The corners of the mesa each comprises a number of surfaces also having slopes of around 45 degrees and one surface having a slope of around 54 degrees. A high-low (N.sup.+ N.sup.- or P.sup.+ P.sup.-) junction is disposed within the mesa and makes a continuous line intercept with the mesa side walls around the entire periphery of the mesa. Except for exceptionally small deviations of no great significance, the high low junction intercept is at a constant height location entirely around the mesa periphery. The mesa is formed by anisotropic etching using a mask having main sides disposed at an angle of at least around 12 degrees to the <111> directions and rounded corners.

REFERENCES:
patent: 3768150 (1973-10-01), Sloan, Jr. et al.
Adolph Blicher, Field-Effect and Bipolar Power Transistor Physics, Academic Press, p. 282, 1981.
B. Jayant Baliga, Modern Power Devices, Krieger Publishing Company, p. 1, 1992.
Dr. Stanley Wolf, Silicon Processing For The VLSI Era, Lattice Press, pp. 1-3, 1986.

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