Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays
Reexamination Certificate
1998-06-04
2003-01-07
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
C257S203000, C257S356000
Reexamination Certificate
active
06504186
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device provided with a library of standard cells which include MOS transistors and the gates of the MOS transistors have not undergone plasma damages. The present invention also relates to a method of designing such a semiconductor device.
More specifically, the present invention relates to a structure of a semiconductor devise and a method of designing such a structure which prevents gates of MOS transistors from undergoing plasma damage in a wafer process in fabricating a semiconductor device.
2. Background Art
FIG. 23
is a plan view showing a conventional standard cell layout pattern employed in auto-placement and auto-routing for a semiconductor device comprising a plurality of standard cells. Referring to
FIG. 23
, a standard cell has an n-type well
3
formed in a p-type silicon substrate
1
. A p-type diffused region
4
is formed in the n-type well
3
. An n-type diffused region
5
is formed in the p-type silicon substrate
1
. A polysilicon wiring line
8
, including gate electrodes
8
g
, is formed on the gate insulating film (not shown) on the wafer
1
. Thus, MOS transistors T
1
and T
2
are formed. The polysilicon wiring line
8
is connected through a contact hole
11
to a metal wiring line
10
, which serves as an input terminal or an input line.
In the conventional standard cell for auto-placement and auto-routing in a gate array and cell base type semiconductor devise, a pattern of the metal wiring line
10
connected to the gates of a MOS transistor T
1
or T
2
is used as an input terminal or an input line.
In the above-mentioned conventional configuration, a wiring line connected to the input terminal
10
or the input line may be long and run outside the conventional standard cell. In that case, the gate oxide film of the MOS transistor T
1
or T
2
is liable to be damaged by electrons launched from a plasma into the metal wiring line during wafer processing such as an etching of the metal wiring line or a removal of the resist. This eventually has resulted in a deterioration of the transistor characteristics.
SUMMARY OF THE INVENTION
The present invention has been made to solve the foregoing problems in the prior art, and it is therefore an object of the present invention to provide a semiconductor device comprising MOS transistors having gates not damaged by a plasma. Another object of the present invention is to provide a method of designing and fabricating such a semiconductor device.
According to one aspect of the present invention, a semiconductor device has a library of standard cells formed on a substrate. Each of the standard cell includes at least a MOS transistor and an input line for the MOS transistor. The semiconductor device further comprises a diffused region formed in the substrate, an insulating layer formed on the substrate, a metallic layer formed on the insulating layer, and a contact portion connecting the metallic layer with the diffused region through the insulating layer.
In another aspect of the present invention, in the semiconductor device, the metallic layer is divided in two portions, and each of the portions is connected to the diffused region through the insulating layer.
In another aspect of the present invention, in the semiconductor device, the diffused region is silicidized.
In another aspect of the present invention, in the semiconductor device, the input line is connected with the metallic layer.
In another aspect of the present invention, in the semiconductor device, the input line is divided in two sides, and each of the two sides is connected to each of the two portions of the metallic layer respectively.
In another aspect of the present invention, in the semiconductor device, an auxiliary cell is formed by the diffused layer, the insulating layer, the metallic layer, and the contact portion.
In another aspect of the present invention, in the semiconductor device, a plurality of the auxiliary cells are provided as a library.
In another aspect of the present invention, in the semiconductor device, the auxiliary cell is formed as a transmission gate including at least a MOS transistor.
In another aspect of the present invention, in the semiconductor device, the transmission gate is comprised of a PMOS transistor and a NMOS transistor.
In another aspect of the present invention, in the semiconductor device, the transmission gate has an input terminal and an output terminal electrically connected to each other.
According to another aspect of the present invention, in a method of designing a semiconductor device, a library of standard cells including at least a MOS transistor is disposed on a substrate by using a software tool including either a symbolic layout tool or a module generator tool. Further, a plurality of diffused regions is disposed on the semiconductor substrate so that each gate of the MOS transistor may be connected to a selected one of the diffused regions.
Other and further objects, features and advantages of the invention will appear more fully from the following description.
REFERENCES:
patent: 3943551 (1976-03-01), Skorup
patent: 4161662 (1979-07-01), Malcolm et al.
patent: 4484212 (1984-11-01), Komatsu et al.
patent: 4568961 (1986-02-01), Noto
patent: 4893157 (1990-01-01), Miyazawa et al.
patent: 5031019 (1991-07-01), Kosaka et al.
patent: 5166770 (1992-11-01), Tang et al.
patent: 5214299 (1993-05-01), Gal et al.
patent: 5605854 (1997-02-01), Yoo
patent: 5700722 (1997-12-01), Sumi
patent: 5760445 (1998-06-01), Diaz
patent: 5844282 (1998-12-01), Noguchi
patent: 19 49 484 (1978-02-01), None
patent: 31 43 565 (1983-05-01), None
patent: 2 113 915 (1983-08-01), None
patent: 63-226111 (1988-09-01), None
patent: 5-36950 (1993-02-01), None
patent: 6-216252 (1994-08-01), None
Ajioka Yoshihide
Hamada Hideyuki
Kanamoto Toshiki
Shimazu Yukihiko
Crane Sara
Mitsubishi Denki & Kabushiki Kaisha
LandOfFree
Semiconductor device having a library of standard cells and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having a library of standard cells and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having a library of standard cells and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3062871