Semiconductor device having a leading wiring layer

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S108000, C438S617000, C438S618000, C438S621000, C257SE21502, C257SE21508, C257SE23021, C257SE23124, C257SE23194

Reexamination Certificate

active

07445958

ABSTRACT:
A manufacturing method of a semiconductor device, comprising the steps of forming an insulation layer, which has an opening section in an area including an area on an electrode pad, on a top surface of the semiconductor substrate on which the electrode pad is formed; at least forming a first barrier metal layer, which becomes a part of a leading wiring layer, in an inner peripheral surface of the opening section including the top surface of the electrode pad; at least forming a main conductor layer, which becomes a part of the leading wiring layer, in an area surrounded by the first barrier metal layer in the opening section; eliminating an upper portion of the main conductor layer at least to a position at which the first barrier metal layer is exposed, and forming a second barrier metal layer, which becomes a part of the leading wiring layer, so as to cover the whole top surface of the main conductor layer.

REFERENCES:
patent: 4836883 (1989-06-01), Hatcher, Jr.
patent: 5293071 (1994-03-01), Erdos
patent: 5451551 (1995-09-01), Krishnan et al.
patent: 5523626 (1996-06-01), Hayashi et al.
patent: 5604379 (1997-02-01), Mori
patent: 5731228 (1998-03-01), Endo et al.
patent: 6083820 (2000-07-01), Farnworth
patent: 6110648 (2000-08-01), Jang
patent: 6111317 (2000-08-01), Okada et al.
patent: 6187615 (2001-02-01), Kim et al.
patent: 6218281 (2001-04-01), Watanabe et al.
patent: 6376353 (2002-04-01), Zhou et al.
patent: 6413851 (2002-07-01), Chow et al.
patent: 6445069 (2002-09-01), Ling et al.
patent: 6455408 (2002-09-01), Hwang et al.
patent: 6472763 (2002-10-01), Fukuda et al.
patent: 6479900 (2002-11-01), Shinogi et al.
patent: 6515372 (2003-02-01), Narizuka et al.
patent: 6551872 (2003-04-01), Cunningham
patent: 6569767 (2003-05-01), Fujisawa et al.
patent: 6576381 (2003-06-01), Hirano et al.
patent: 6656758 (2003-12-01), Shinogi et al.
patent: 6656828 (2003-12-01), Maitani et al.
patent: 6713381 (2004-03-01), Barr et al.
patent: 6835595 (2004-12-01), Suzuki et al.
patent: 2002/0004257 (2002-01-01), Takaoka et al.
patent: 2002/0014705 (2002-02-01), Ishio et al.
patent: 10-261663 (1998-09-01), None

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor device having a leading wiring layer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device having a leading wiring layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having a leading wiring layer will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4039813

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.