Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2007-06-26
2007-06-26
Andujar, Leonardo (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S499000, C257S506000, C257SE23151
Reexamination Certificate
active
11190854
ABSTRACT:
Over a memory cell array region of a static RAM (random access memory), dummy wire patterns are formed such that each dummy wire pattern covers 2×2 horizontally and vertically-adjacent intersection points of word lines and bit lines, and horizontally-running wire channels and vertically-running wire channels are formed between the dummy wire patterns in a lattice configuration. Then, a signal line is automatically arranged to extend through any of the wire channels. The dummy wire patterns are provided in a layer lying on the word lines, and the signal line is provided as a metal line extending in the same layer as that of the dummy wire patterns.
REFERENCES:
patent: 2003/0038653 (2003-02-01), Ooishi et al.
patent: 1-272149 (1989-10-01), None
patent: 2001-257266 (2001-09-01), None
Andujar Leonardo
McDermott Will & Emery LLP
Quinto Kevin
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