Semiconductor device having a latch circuit for latching data ex

Details Semiconductor device having a latch circuit for latching data ex Semiconductor device having a latch circuit for latching data ex

1998-05-15

1999-03-23

Nelms, David

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Regenerating or restoring rectangular or pulse waveform

327176, 327291, 36518905, 365233, G11C 1134

Patent

active

058865535

ABSTRACT:
To use a high performance central processing unit (CPU)(e.g., operating with high frequency), a memory system includes a memory cell array having a plurality of word lines connected to memory cells, a latch circuit for receiving and latching a first control signal in response to a first clock signal and for outputting a second control signal, and a decoder for selecting one word line among the word lines in response to an address signal when the decoder receives the second control signal. The latch circuit includes a first latch portion for latching the first control signal during a first cycle of the first clock signal, and a second latch portion for latching the first control signal during a second cycle of the first clock signal.

REFERENCES:
patent: 5083296 (1992-01-01), Hara et al.
patent: 5515325 (1996-05-01), Wada
patent: 5521878 (1996-05-01), Ohtani et al.
patent: 5521879 (1996-05-01), Takasugi
patent: 5539693 (1996-07-01), Koshikawa et al.
patent: 5610864 (1997-03-01), Manning
patent: 5726950 (1998-03-01), Okamoto et al.
Japanese Office Action dated Jun. 1998 with partial translation.

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