Semiconductor device having a hollow region and method of...

Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – Groove

Reexamination Certificate

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C257S410000

Reexamination Certificate

active

07075169

ABSTRACT:
A hollow region is formed in a silicon substrate. A plurality of openings formed in the silicon layer on the hollow region is filled with a buried film. The bottom portion of the hollow region is formed with a plurality of silicon pillars, which support the silicon layer.

REFERENCES:
patent: 5554870 (1996-09-01), Fitch et al.
patent: 5654573 (1997-08-01), Oashi et al.
patent: 6118164 (2000-09-01), Seefeldt et al.
patent: 6277703 (2001-08-01), Barlocchi et al.
patent: 6380010 (2002-04-01), Brigham et al.
patent: 6531754 (2003-03-01), Nagano et al.
patent: 6570217 (2003-05-01), Sato et al.
patent: 6630714 (2003-10-01), Sato et al.
patent: 6642115 (2003-11-01), Cohen et al.
patent: 6670675 (2003-12-01), Ho et al.
patent: 2004/0124439 (2004-07-01), Minami et al.
patent: 10-321802 (1998-12-01), None
patent: 2000-12858 (2000-01-01), None
patent: 2000-35609 (2000-02-01), None
patent: 2003-31687 (2003-01-01), None
T. Sato, et al., International Electron Devices Meeting, pp. 517-520, “A New Substrate Engineering for the Formation of Empty Space in Silicon (ESS) Induced by Silicon Surface Migration”, Dec. 5-8, 1999.
T. Sato, et al., International Electron Devices Meeting, pp. 809-812, “SON (Silicon on Nothing) MOSFET Using ESS (Empty Space in Silicon) Technique for SoC Applications”, Dec. 2-5, 2001.
U.S. Appl. No. 10/237,206, filed Sep. 9, 2002, Nagano et al.
U.S. Appl. No. 10/407,677, filed Apr. 7, 2003, Nagano et al.
U.S. Appl. No. 10/439,896, filed May 16, 2003, Nagano et al.
U.S. Appl. No. 09/650,748, filed Aug. 30, 2001, Sato et al.
U.S. Appl. No. 09/960,333, filed Sep. 24, 2001, Minami et al.
U.S. Appl. No. 09/995,594, filed Nov. 29, 2001, Yamada et al.
U.S. Appl. No. 10/078,344, filed Feb. 21, 2002, Nagano et al.
U.S. Appl. No. 10/096,655, filed Mar. 14, 2002, Yamada et al.
U.S. Appl. No. 10/654,030, filed Sep. 4, 2003, Minami et al.
U.S. Appl. No. 10/665,614, filed Sep. 19, 2003, Inoh et al.
U.S. Appl. No. 10/654,030, filed Sep. 4, 2003, Minami et al.
U.S. Appl. No. 11/097,166, filed Apr. 4, 2005, Yamada.

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