Semiconductor device having a fuse layer

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics

Reexamination Certificate

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C257S209000, C365S096000, C365S225700

Reexamination Certificate

active

06259147

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and more specifically to the structures of semiconductor devices having a fuse layer disconnected through light radiation so as to control a redundant circuit.
2. Description of the Background Art
It has been well known to provide a redundant circuit for recovering semiconductor devices from defects. In general, a fuse layer is formed together with the redundant circuit. The fuse layer that is disconnected as appropriate allows a defective circuit to be replaced by the redundant circuit. A semiconductor device with such a fuse layer is disclosed e.g. in U.S. Pat. No. 5,589,706.
FIG. 19
shows a schematic configuration of a dynamic random access memory (DRAM) as one example of a semiconductor device with a redundant circuit. Referring to
FIG. 19
, a memory cell array
20
includes a word line WL extending in a row direction from a row decoder
21
via a word driver
22
, and a bit line BL extending in a column direction from a column decoder
23
. Word line WL and bit line BL are crossed with each other. A memory cell MC is provided at a crossing of word line WL and bit line BL.
Outside word line WL, a spare word line SWL extends in the row direction from a spare decoder
24
via a spare word driver
25
. A spare memory cell SMC is provided at a crossing of spare word line SWL and each bit line BL.
Spare memory cell SMC, spare decoder
24
and spare word driver
25
configure a redundant circuit. Spare decoder
24
connects with a defective-address comparing circuit
26
in which a fuse layer is formed. The fuse layer controls the redundant circuit. Defective-address comparing circuit
26
receives row addresses.
FIG. 20
shows a fuse layer of a DRAM configured as above and a vicinity of the fuse layer in cross section.
Referring to
FIG. 20
, a fuse layer
3
is formed on a semiconductor substrate
1
, with an interlayer insulation film
2
interposed therebetween. Fuse layer
3
is covered by an insulation layer
4
formed e.g. of silicon oxide film.
A defective circuit is recovered by disconnecting fuse layer
3
configured as described above. In general, laser light is employed to disconnect fuse layer
3
. The principle of the disconnection of fuse layer
3
through laser light will now be described.
Referring again to
FIG. 20
, laser light
5
illuminates fuse layer
3
. Thus, laser light
5
is absorbed by fuse layer
3
and fuse layer
3
is thus heated. Consequently, fuse layer
3
changes in phase from solid to liquid to gas. Thus, the evaporation pressure of fuse layer
3
pushes isolation layer
4
upwards to create a crack
9
in isolation layer
4
, as shown in FIG.
21
.
When the evaporation pressure of fuse layer
3
exceeds a predetermined value, fuse layer
3
is disconnected and insulation layer
4
overlying fuse layer
3
is blown away to create a blow trace
4
a
, as shown in FIG.
22
.
Conventional fuse layers are often designed in view of electrical characteristics, processing convenience and the like. Accordingly, in shifting to semiconductor devices having a structure of a new generation, a member totally different from that of the previous generation can be adopted as a fuse layer, a plurality of fuse layers provided can each have a different dimension, and each fuse layer can be surrounded by an oxide film having a different thickness. As a result, blow traces created by fuse layer disconnection cannot have a uniform dimension and this results in a disadvantage that a fuse layer can not be disconnected reliably.
Furthermore, it has been increasingly difficult to disconnect an underlying fuse layer due to high integration of elements configuring a semiconductor device and to an increased film thickness associated with a reduced number of the steps of the process for manufacturing the same. Currently, an interconnection layer located as high as possible is increasingly used as a fuse layer.
The interconnection layer located as high as possible is formed mainly of metal material. It has been known, however, that metal material increases the reflection of illumination light from the interconnection layer in transferring an interconnection pattern onto the interconnection layer and the interconnection pattern cannot be transferred satisfactorily. To address this disadvantage, a film is provided on the surface of the interconnection layer to reduce the reflection of illumination light.
An anti-diffusion film is also provided between the semiconductor substrate and the interconnection layer of metal to prevent the ions of the silicon of the semiconductor substrate from diffusing into the interconnection layer. From the reason provided above, a three-layered structure is frequently used for the interconnection layer adopted as a fuse layer.
The fuse layer structured of three layers is, however, structurally not preferable in disconnecting the fuse layer. Furthermore, the region provided with the fuse layer is lower in interconnection density than a memory region. As a result, if the process for forming an interconnection layer in the memory region is similar to that for forming an interconnection layer in the fuse layer, the cross section of the fuse layer varies from location to location due to the low interconnection density.
Furthermore, when the beam wavelength of the laser light illuminating the fuse layer is approximately equal in dimension to the width of the fuse layer and the beam diameter of the laser light is larger than the width of the fuse layer, the profile of the light absorbed by the fuse layer significantly depends on the shape of the fuse layer and this results in a very complicated profile of the light absorbed by the fuse layer.
The laser light absorption into the fuse layer allows the optical energy of the laser light to be transformed into thermal energy so that the fuse layer changes in phase from solid to liquid to gas and the fuse layer is thus disconnected. While the light-absorption profile corresponds to heat-emission profile, it is difficult to reliably disconnect the fuse layer and obtain a smaller blow trace depending on the structure of the fuse layer when the heat-emission profile of the fuse layer is a profile which is not suitable for disconnecting the fuse layer.
SUMMARY OF THE INVENTION
The present invention has been made to overcome the disadvantages described above.
One object of the present invention is to provide a semiconductor device having a fuse layer capable of being disconnected reliably and providing a smaller blow trace.
Another object of the present invention is to miniaturize the semiconductor device.
A semiconductor device according to the present invention includes a first insulation layer, a plurality of fuse layers extending on the insulation layer in one direction and disconnected through light illumination to control a redundant circuit, a pseudo fuse layer provided on the first insulation layer along at least one side of the fuse layer, a second insulation layer formed to cover the fuse layers and the pseudo fuse layer, and a protection film formed on the second insulation layer and having an opening at a region opposite to the fuse layers. The fuse layers have a spacing of less than 4 &mgr;m or 4.5 &mgr;m to 5.5 &mgr;m.
In transferring an interconnection pattern for the fuse layers, the pseudo fuse layer thus provided allows any deformation in cross section of the interconnection pattern that would be otherwise caused at a surface of low interconnection density to be caused at the pseudo fuse layer rather than the fuse layers. Since the pseudo fuse layer is not disconnected through light illumination, there will not be any disadvantage caused if such a deformation of an interconnection pattern is caused at the pseudo fuse layer.
In the fuse layer disconnection, the fuse layers that are uniformed in cross section and have a spacing of less than 4 &mgr;m or 4.5 &mgr;m to 5.5 &mgr;m can allow for reliable disconnection of the fuse layers and uniform blow traces.
Preventing the enlargement of

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