Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Reexamination Certificate
2000-02-28
2002-04-16
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
C438S601000
Reexamination Certificate
active
06372556
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and fabricating method thereof. More particularly, the invention is directed to a semiconductor device that includes a fuse for re-routing circuit paths and to a method of making the semiconductor device. The present invention allows for a high integration of the semiconductor device by having the fuse formed on top of a metal conductor.
DESCRIPTION OF THE RELATED ART
When a defect is detected in any of the plurality of the fine cells of a semiconductor device, e.g. a complex semiconductor device or a semiconductor memory device, during fabrication, the device is deemed defective. This is because the defective cells will cause a malfunction in the semiconductor device. Even if a defect is found in only part of the semiconductor device, the whole device is classified as defective and destroyed as defective goods. This significantly decreases the productive yield of final products.
Currently, memory devices are embedded with redundant cells that are used for replacing any defective cells, thereby saving the entire semiconductor memory device and improving the overall product yield. Using redundant cells involves installing spare rows and columns at predetermined intervals during the manufacturing process. The defective cells are removed from their respective row and column locations and are replaced with spare memory cells. In other words, if a defective cell is detected during a wafer-level test, a program is run for changing the address of the defective cell to an address of a spare cell. Therefore, when the address of a defective cell line is actually requested, a spare cell line is selected instead of the defective cell line. One of the programming methods for changing the addresses of the cells involves cutting a fuse with a laser beam. The fuse is usually made on a metal layer in the semiconductor device.
FIGS. 1 and 2
are views illustrating the structure of a conventional semiconductor device having a fuse, where
FIG. 2
is a cross-sectional view illustrating the structure taken along the A—A line shown in
FIG. 1. A
semiconductor device includes a substrate
10
, a plurality of interlevel insulating layers
14
,
18
,
24
, and a plurality of metal wires
12
,
16
,
22
. A fuse pattern
28
is formed on the third interlevel insulating layer
24
and comprises a fuse metal layer
28
a
. A conductive plug
20
electrically connects the second metal wire
16
with the third metal wire
22
. After the fuse pattern
28
and the metal wire
26
are formed on the third interlevel insulating layer
24
, protection layers
29
and
30
are then formed on the resulting structure.
The fuse pattern
28
comprises a deposition structure having a fuse metal layer and a wiring metal layer. The structure is arranged on the insulating plate
24
and is integrally connected with the metal wire
26
on the uppermost layer. Fuse I is formed from a portion of the fuse pattern
28
and is made in a single structure with an open fuse window W.
When a fuse metal layer
28
a
is formed on the insulating plate over the metal wires
12
,
18
,
24
for the purpose of improving the integration of the device, thermal damage can occur to the metal wires positioned under the fuse. That is, when using a laser beam to cut the fuse, the underlying metal wires may be damaged by the thermal energy of the laser beam. Consequently, the reliability of the metal wires can be greatly reduced. Therefore, there is an urgent need to improve the structure of the semiconductor device containing a fuse and solve the aforementioned problems.
SUMMARY OF THE INVENTION
Therefore, a feature of the present invention is to provide a semiconductor device having a fuse and a heat blocking layer which is larger than a fuse window. The heat blocking layer is placed under a fuse metal layer. Even if a metal wire were to be placed under the fuse metal layer, thermal damage can be prevented when the fuse is cut by a laser beam. As a result, a fuse can be formed on the metal wire while achieving a high integration of the semiconductor device.
Another feature of the present invention includes a semiconductor device comprising: a first insulating layer which comprises a predetermined metal wire therein; a second insulating layer which comprises a heat blocking layer therein, wherein the heat blocking layer is positioned over the predetermined metal wire; and an upper layer which comprises a deposition structure having a fuse metal layer and a wiring metal layer, the fuse metal layer comprises a fuse pattern that is to be used as a fuse and is exposed via a fuse window in the upper layer, wherein the fuse pattern is electrically connected to the wiring metal layer, and the heat blocking layer is positioned under the fuse metal layer and is larger than the fuse window.
Still another feature of the present invention is to provide a method for fabricating a semiconductor device having a fuse, comprising the steps of forming a first interlevel insulating layer on a semiconductor substrate having a first metal wire, forming a second metal wire on the first interlevel insulating layer, forming a second interlevel insulating layer on the first interlevel insulating layer, forming a hole and a grooved portion for exposing a surface of the second metal wire embedded in the second interlevel insulating layer by selectively etching out a first predetermined region and a second predetermined region of the second interlevel insulating layer, respectively, forming a conductive plug in the hole and a heat blocking layer in the grooved portion from a metal, forming a third metal wire on the second interlevel insulating layer for connection with the conductive plug, forming a third interlevel insulating layer on the second interlevel insulating layer, simultaneously forming a fuse pattern in a deposition structure of a,fuse metal layer and a wiring metal layer on the third interlevel insulating layer, and forming a fourth metal wire for connection with a lateral edge of the fuse pattern.
The present invention will now be described fully hereinafter with reference to the accompanying drawings, in which the preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It is also to be understood that when a layer is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present.
The invention may be understood and its features will become apparent to those skilled in the art by reference to the accompanying drawings as follows.
REFERENCES:
patent: 4210464 (1980-07-01), Tanaka et al.
patent: 6016001 (2000-01-01), Sanchez et al.
patent: 6168984 (2001-01-01), Yoo et al.
Dang Phuc T.
Nelms David
The Law Offices of Eugene M. Lee P.L.L.C.
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