Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2001-01-23
2002-11-26
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S211000
Reexamination Certificate
active
06486558
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a dummy pattern, and more particularly, to a semiconductor device having a memory cell block including a plurality of memory cells.
2. Description of the Background Art
A semiconductor device, such as a memory device, has a memory cell block comprising a plurality of memory cells. A plurality of memory cells included in a memory cellblock are formed by means of repetition of an identical pattern. As the area of the memory cell block becomes wider, the environment of memory cells located at the center of the memory cell block becomes apt to greatly differs from the environment of memory cells located in the vicinity of the periphery of the memory cell block. An example of such a difference in environment of memory cells will be described by reference to
FIGS. 8A through 8D
.
FIGS. 8A through 8D
are enlarged cross-sectional views showing the outermost periphery portion of a memory cell block formed on a conventional semiconductor device.
As shown in
FIG. 8A
, according to a conventional method of manufacturing a semiconductor device, a thermal oxide film
12
having a thickness of about 15 nm, a polysilicon film
14
having a thickness of about 50 nm, and a nitride film
16
having a thickness of about 165 nm are deposited, in this sequence, on a silicon substrate
10
. These films are patterned by means of photolithography and etching. Trenches
18
having a depth of about 300 nm are formed in the silicon substrate
10
by means of etching while the thus-patterned nitride film
16
and the like are taken as a mask.
An oxide layer is formed to a thickness of about 50 nm on the interior walls of the respective trenches
18
by means of thermal oxidation of the silicon substrate
10
. As shown in
FIG. 8B
, in order to fill each of the trenches
18
with an oxide film, an oxide film
20
is deposited to a thickness of about 500 nm over the entire surface of the silicon substrate
10
. Because of its characteristics, the oxide film
20
is deposited thickly on a narrow pattern and thinly on a wide pattern. For this reason, the thickness of the oxide film
20
becomes thinner toward the periphery of the memory cell block relative to the thickness in the center thereof.
As shown in
FIG. 8C
, according to the conventional method, the entire surface of the silicon substrate
10
is abraded by means of chemical-and-mechanical polishing (CMP). As illustrated, irregularities arising in the thickness of the oxide film
20
before CMP operation are not absorbed by CMP operation, and the irregularities still remain after the CMP process.
As shown in
FIG. 8D
, the nitride film
16
, the polysilicon film
14
, and the thermal oxide film
12
remaining on the surface of the silicon substrate
10
are removed after the CMP operation. As a result, an isolation oxide film
22
for separating individual active regions from each other is formed on the surface of the silicon substrate
10
. Irregularities in the thickness of the oxide film
20
which have remained after the CMP operation still remain as irregularities in the thickness of the isolation oxide film
22
. As a result, the isolation oxide film
22
surrounding the outermost periphery portion of a memory cell block becomes thinner than the isolation oxide film
22
located in the vicinity of the center of the memory cell block.
After formation of the isolation oxide film
22
, a gate dielectric film is formed to a thickness of 30 to 100 angstroms on the surface of the silicon substrate
10
. Subsequently, a gate electrode made of polysilicon is patterned onto the gate dielectric film. Further, a side wall dielectric film is formed from TEOS or a nitride film so as to cover the side wall of a gate electrode.
According to the conventional method for manufacturing a semiconductor device, the isolation oxide film
22
is also removed during an etching process for forming a gate electrode or a side wall dielectric film on the silicon substrate
10
. As mentioned above, the thickness of the isolation oxide film
22
surrounding the outermost periphery portion of the memory cell block tends to becomes smaller than the thickness of the isolation oxide film
22
located in the vicinity of the center of the memory cell block. Because of such a tendency, the isolation oxide film
22
surrounding the outermost periphery portion of the memory cell block may becomes lower than the surface of the silicon substrate
10
under the influence of the foregoing various etching operations.
In the area where the surface of the isolation oxide film
22
is lower than the surface of the silicon substrate
10
, the resistance to a junction leakage is deteriorated. For this reason, in the conventional semiconductor device, the memory cells located along the outermost periphery of the memory cell block are susceptible to failures ascribable to a junction leakage. Thus, in the semiconductor device having a memory cell block, the environment of memory cells located in the vicinity of the center of the memory cell block greatly differs from the environment of memory cells located in the vicinity of the periphery of the memory cell block. Hence, anomalies are likely to arise mainly in the memory cells located in the vicinity of the outermost periphery of the memory cell block.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve the foregoing drawbacks of the conventional methods and is aimed at providing a semiconductor device having a structure suitable for imparting a stable characteristic to all memory cells provided in a memory cell block.
The above objects of the present invention are achieved by a semiconductor device described below. The semiconductor device includes a plurality of impurity-diffused layers provided on a silicon substrate at predetermined intervals. One or some of the plurality of impurity-diffused layers located at the outermost periphery position are dummy diffusion layers which are functionally not required by the semiconductor device.
The above objects of the present invention are also achieved by a semiconductor device described below. The semiconductor device includes constituent elements of the same kind which are provided in a plurality of layers. The semiconductor device also includes dummy patterns such that the constituent elements are provided in substantially identical proportions in the plurality of layers. Interconnection elements are provided for fixing the electric potential of the dummy patterns to a predetermined electric potential.
The above objects of the present invention are further achieved by a semiconductor device described below. The semiconductor device includes dummy patterns formed such that constituent elements are provided in a predetermined layer so as to assume a uniform density or pitch over the entire surface of the predetermined layer. The semiconductor device also includes interconnection elements for fixing the electric potential of the dummy patterns to a predetermined electric potential.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
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patent: 5923947 (1999-07-01), Sur
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Sugiyama Masao
Yoshiyama Kenji
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
Tran Long K.
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