Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-02-02
2004-01-20
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S640000, C257S760000, C257S774000, C438S634000, C438S740000
Reexamination Certificate
active
06680537
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing same. More particularly, the invention relates to a semiconductor device having a contact or via hole formed through a first interlayer film on a semiconductor substrate and an interconnect trench formed through a second interlayer film over the first interlayer film in a manner opened to the contact or via hole so that a conductive material is buried inside the contact or via hole and the interconnect trench, and a method for manufacturing the same device.
2. Description of the Prior Art
There is disclosed a semiconductor device of this kind which is manufactured through utilizing a dual damascene process, for example, in Japanese Patent Publication No. H5-46983. The semiconductor device
1
according to the prior art is shown in FIG.
1
.
The semiconductor device in
FIG. 1
includes a semiconductor substrate
2
. On the semiconductor substrate
2
are formed, in order, a first interlayer film
3
a
, an etch stop film
3
b
and a second interlayer film
3
c
. A contact or via hole
5
a
is formed through the first interlayer film
3
a
and the etch stop film
3
b
so that the hole
5
a
is opened to a conductive region
4
formed in a surface of the semiconductor substrate
2
. Meanwhile, an interconnect trench
5
b
is formed through the second interlayer film
3
c
including a region around and above the contact hole
5
a
. A metal interconnect
6
is buried inside the contact hole
5
a
and the interconnect trench
5
b
. Incidentally, the etch stop film
3
b
also serves to prevent copper (Cu), etc. forming the metal interconnect
6
from diffusing outside.
To manufacture such a semiconductor device as shown in
FIG. 1
, a conductive region
4
is formed in a surface of the semiconductor substrate
2
with polysilicon or the like, as shown in
FIG. 2A. A
first interlayer film
3
a
and an etch stop layer
3
b
are formed over the semiconductor substrate
2
, and a window
7
is formed through the etch stop film
3
b
. Subsequently, a second interlayer film
3
c
is formed over the etch stop film
3
b
, as shown in FIG.
2
B. Then the first interlayer film
3
a
, together with the second interlayer film
3
c
, are masked by and etched through patterned photoresist
8
, thereby forming a contact hole
5
a
as well as an interconnect trench
5
b
, as shown in FIG.
2
C.
After removing the photoresist
8
, a metal interconnect
6
is formed by burying an inside of the contact hole
5
a
and the interconnect trench
5
b
with copper (Cu), aluminum (Al) or the like, as shown in FIG.
2
D. The metal interconnect
6
at its unwanted portions is removed by implementing a CMP (Chemical-Mechanical Polish) process.
The conventional semiconductor device
1
has required an etch stop film
3
b
as stated above. However, this results in a problem in the manufacturing process due to a complicated three-layered structure despite the interconnect trench
5
b
can be formed even in depth.
SUMMARY OF THE INVENTION
It is therefore a primary object of the present invention to provide a novel semiconductor device and manufacturing method therefor.
It is another object of the present invention to provide a semiconductor device and manufacturing method by which simplification is available for the device structure.
A semiconductor device according to the present invention comprises: a first interlayer film; a contact hole formed through the first interlayer film by etching the first interlayer film; a second interlayer film formed over a surface of the first interlayer film; and an interconnect trench formed through the second interlayer film by etching the second interlayer film and opened to the contact hole, wherein the first interlayer film has an etch rate lower than an etch rate of the second interlayer film.
The first interlayer film is formed, for example, of SiN, and accordingly lower in etch rate than the second interlayer film. Due to this, the first interlayer film behaves as an etch stop during etching the second interlayer film. Therefore there is no necessity of separately providing an etch stop film between the first interlayer film and the second interlayer film. According to this invention, it is possible to simplify the device structure and hence the manufacture process.
If the first interlayer film is formed by a nitride film having a high molecular density, the first interlayer film can be utilized also as a diffusion prevention film.
The first etching process and the second etching process may be in a common process or separate process from each other.
A method for manufacturing a semiconductor device according to the present invention, comprises the steps of: forming a first interlayer film over a semiconductor substrate; forming a second interlayer film over a surface of the first interlayer film; etching the second interlayer film by utilizing the first interlayer film as an etch stop to thereby form an interconnect trench; and etching the first interlayer film to form a contact hole opened to the interconnect trench.
Another method for manufacturing a semiconductor device according to the present invention, comprises the steps of: forming a first interlayer film over a semiconductor substrate; etching the first interlayer film to form a contact hole; forming a second interlayer film on a surface of the first interlayer film; and etching the second interlayer film by utilizing the first interlayer film as an etch stop to thereby form an interconnect trench opened to the contact hole.
In either manufacturing method, the first interlayer serves as not only a layer to form a contact or via hole but also an etch stop layer in etching the second interlayer film. Accordingly, there is no necessity to separately provide an etch stop layer over the first interlayer film, thus simplifying the manufacturing process.
REFERENCES:
patent: 5461004 (1995-10-01), Kim
patent: 5528081 (1996-06-01), Hall
patent: 5600182 (1997-02-01), Schinella
patent: 5614765 (1997-03-01), Avanzino et al.
patent: 5635423 (1997-06-01), Huang et al.
patent: 5648298 (1997-07-01), Cho
patent: 5686354 (1997-11-01), Avanzino et al.
patent: 5703403 (1997-12-01), Sobue et al.
patent: 5705430 (1998-01-01), Avanzino et al.
patent: 5741626 (1998-04-01), Jain et al.
patent: 5773890 (1998-06-01), Uchiyama et al.
patent: 5801094 (1998-09-01), Yew et al.
patent: 5808365 (1998-09-01), Mori
patent: 5850102 (1998-12-01), Matsuno
patent: 5852328 (1998-12-01), Nishimura et al.
patent: 5880519 (1999-03-01), Bothra et al.
patent: 5883433 (1999-03-01), Oda
patent: 5889302 (1999-03-01), Liu
patent: 5960320 (1999-09-01), Park
patent: 6027994 (2000-02-01), Huang et al.
patent: 6028359 (2000-02-01), Merchant et al.
patent: 6054768 (2000-04-01), Givens et al.
patent: 6077772 (2000-06-01), Park et al.
patent: 6081034 (2000-06-01), Sandhu et al.
patent: 6091148 (2000-07-01), Givens et al.
patent: 6133139 (2000-10-01), Dalal et al.
patent: 6180512 (2001-01-01), Dai
patent: 6319820 (2001-11-01), Liu
patent: 5-46983 (1993-07-01), None
Bodner Gerald T.
Eckert George
Ortiz Edgardo
Rohm & Co., Ltd.
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