Semiconductor device having a compressed device isolation...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C438S221000, C438S424000, C438S435000, C257SE21002

Reexamination Certificate

active

07541259

ABSTRACT:
The semiconductor device includes a lower device isolation structure formed in a semiconductor substrate to define an active region. The lower device isolation structure has a first compressive stress. An upper device isolation structure is disposed over the lower device isolation structure. The upper device isolation structure has a second compressive stress greater than the first compressive stress. A gate structure is disposed over the active region between the neighboring upper device isolation structures.

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patent: 1019970008482 (1997-05-01), None
patent: 1998-084173 (1998-12-01), None
patent: 1020060000483 (2006-01-01), None
patent: WO 98/43293 (1998-10-01), None

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