Semiconductor device having a chip—chip structure

Details Semiconductor device having a chip—chip structure Semiconductor device having a chip—chip structure

2007-02-13

2007-02-13

Williams, Alexander Oscar (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257SE25013, C257SE23179, C257SE25011, C257SE25012, C257S777000, C257S723000, C257S727000, C257S724000, C257S725000, C257S048000, C257S679000, C257S288000, C257S528000, C257S690000, C257S691000, C257S698000, C714S744000

Reexamination Certificate

active

10713213

ABSTRACT:
A semiconductor device having a chip-on-chip structure wherein; a first semiconductor chip with a memory macro control circuit where a plurality of inter-chip connection terminals and a plurality of external connection terminals are formed on a surface of the chip; and a second semiconductor chip with memory macro having input/output terminals for the normal operation mode and for the test mode where a plurality of inter-chip connection terminals and a plurality of external connection terminals are formed on a surface of the chip; are adhered to each other in a form so that the surfaces of the chips are opposed to each other and so that the inter-chip connection terminals of the first semiconductor chip and the inter-chip connection terminals of the second semiconductor chip are connected to each other; is provided wherein a multiplexer circuit and a demultiplexer circuit are provided with the first semiconductor chip and the second semiconductor chip so that a signal is inputted to, or is outputted from, the memory macro via the common inter-chip connection terminals by switching signal transmission channels in either case, during normal operation mode or during memory macro test mode which is carried out after the connection of the chips.

REFERENCES:
patent: 5646422 (1997-07-01), Hashizume
patent: 5848003 (1998-12-01), Nishikawa
patent: 6523018 (2003-02-01), Louis et al.
patent: 6649931 (2003-11-01), Honma et al.
patent: 2003/0015792 (2003-01-01), Urakawa

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