Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2002-04-08
2003-10-28
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S528000, C257S532000, C438S329000, C438S957000
Reexamination Certificate
active
06639299
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-118242, filed Apr. 17, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a CSP (Chip Size Package) structure, a manufacturing method therefor, and an electronic device having the semiconductor device.
2. Description of the Related Art
Semiconductor devices having a CSP structure in which chip and package sizes are almost equal to each other are recently known and used to increase a mounting density on a circuit board. An example of this structure is shown in FIG.
16
.
FIG. 16
is a sectional view showing a semiconductor device
20
. The semiconductor device
20
has a so-called wafer level CSP structure obtained by dicing, into chips, a wafer having undergone package processing including a protective film formation step, a conductive layer formation step, a post formation step, and a resin encapsulation step.
The semiconductor devices
20
are formed from a wafer. The surface (circuit surface side) of a semiconductor substrate
1
bearing a circuit element or elements has a plurality of connection pads
2
made from aluminum electrodes or the like. A passivation film (insulating film)
3
made of silicon oxide, silicon nitride, or the like is formed on a circuit side of the semiconductor substrate
1
including the upper surfaces of the connection pads
2
so as to expose the center of each connection pad
2
.
A protective film
4
with openings so as to expose the center of each connection pad
2
is formed on the upper surface of the passivation film
3
. The protective film
4
is formed by, e.g., applying a polyimide-based resin to the entire circuit surface side of the wafer
1
, curing the resin, performing resist patterning and protective film patterning with an etching solution, and removing the resist.
Conductive layers
5
electrically connected to the connection pads
2
are formed on the protective film
4
formed in the above manner. Posts
6
made from columnar electrodes are formed at predetermined portions on the conductive layer
5
. An oxide film on a distal end face
6
a
of each post
6
which has been naturally formed is removed and subjected to metallization processing such as solder printing. The post
6
is used to connect a terminal on a circuit board (not shown). The height of the post
6
is at least 50 &mgr;m, and typically about 100 to 150 &mgr;m. The post
6
is formed into a straight shape to absorb a stress generated by the difference in thermal expansion coefficient between the semiconductor substrate
1
and the circuit board.
An encapsulating film
7
made of a resin such as polyimide or epoxy is formed on the entire surface side of the semiconductor substrate
1
between the posts
6
.
A filter circuit and antenna element formed from passive elements are required to implement an RF radio circuit module such as a Bluetooth module or GPS receiving module by using the semiconductor device
20
with the above-described wafer level CSP structure. These passive elements cannot be conventionally mounted inside a chip, and are arranged outside the chip as discrete components. This makes it difficult to further micronize the module.
In such an RF circuit module, the wiring length between components influences frequency characteristics, and is difficult to further shorten. The frequency characteristics are, therefore, difficult to improve further.
BRIEF SUMMARY OF THE INVENTION
The present invention has an advantage capable of mounting, on a chip, passive elements such as an antenna element and capacitive element or a passive circuit formed from them and micronizing the module in a semiconductor device which is obtained by cutting a wafer into chips and has a CSP structure in which chip and package sizes are almost equal. The present invention can provide a mounting structure suitable for an electronic device having a semiconductor device in which an antenna element is mounted on a chip.
To achieve the above advantage, a semiconductor device according to the present invention comprises a first columnar electrode which is electrically connected to at least one first connection pad among a plurality of connection pads on a semiconductor substrate on which a circuit element forming region and the plurality of connection pads are formed, at least one first conductive layer which is connected to at least one second connection pad, an encapsulating film which is formed at least around the first columnar electrode and on the first conductive layer on the semiconductor substrate, and at least one second conductive layer which is formed on the encapsulating film so as to face the first conductive layer. The facing first and second conductive layers can form at least one passive element, e.g., a capacitive element. The semiconductor device further comprises a second columnar electrode which is electrically connected to the second connection pad and is connected to the second conductive layer, and a third columnar electrode which is electrically connected to at least one third connection pad and is connected to the second conductive layer. By using the second connection pad as a ground pad and the third connection pad as a feeding pad, an antenna element, e.g., an inverted F-shaped antenna can be formed as a passive element. The semiconductor device further comprises a plurality of passive elements, and a third conductive layer which is connected between the passive elements and has a thin-film passive element. The passive elements and thin-film passive element can form a passive circuit, e.g., a filter circuit.
A passive element or circuit can be formed on the circuit element forming region of the semiconductor substrate and connected to the circuit element of the semiconductor substrate. A module constituted using this semiconductor device can be micronized.
In an electronic device comprising a semiconductor substrate on which an antenna element is formed in the above way, and a wiring board on which the semiconductor device is mounted and a plurality of wiring patterns are formed, no wiring pattern is formed in a region of the wiring board that faces the second conductive layer of the semiconductor device, or the region is an opening. This structure can suppress degradation in antenna performance, obtaining a high radiation efficiency of radio waves.
To achieve the above advantage, according to a semiconductor device manufacturing method of the present invention, an insulating film is formed in each chip formation region of a semiconductor wafer substrate having a plurality of chip formation regions each having a circuit element forming region and a plurality of connection pads. Then, a first columnar electrode is electrically connected to at least one first connection pad in each chip formation region, and a first conductive layer is formed on the insulating film so as to be connected to at least one second connection pad. After an encapsulating film is formed on the insulating film and first conductive layer, at least one second conductive layer facing the first conductive layer is formed on the encapsulating film in the chip formation region. A passive element such as an antenna element or capacitive element, or a passive circuit such as a filter circuit is formed on the circuit element forming region. Thereafter, the semiconductor wafer substrate is diced into the respective chip formation regions.
This method allows simultaneously forming a plurality of semiconductor devices each having a passive element or circuit on a circuit element forming region.
REFERENCES:
patent: 4617193 (1986-10-01), Wu
patent: 5481131 (1996-01-01), Staudinger et al.
patent: 5874770 (1999-02-01), Saia et al.
patent: 6362525 (2002-03-01), Rahim
patent: 2000-235979 (2000-08-01), None
Casio Computer Co. Ltd.
Flynn Nathan J.
Wilson Scott R
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