Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2000-06-28
2003-09-30
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000, C438S627000, C438S643000
Reexamination Certificate
active
06627462
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device; and, more particularly, to a semiconductor device having a capacitor structure for use in a memory cell and a method for the manufacture thereof.
DESCRIPTION OF THE PRIOR ART
As is well known, a dynamic random access memory (DRAM) with a memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by down-sizing through micronization. However, there is still a demand for downsizing the area of the memory cell.
To meet the demand, therefore, there have been proposed several methods, such as a trench type or a stack type capacitor, which is arranged three-dimensionally in a memory device to reduce the cell area available to the capacitor. However, the process of manufacturing three-dimensionally arranged capacitor is a long and tedious one and consequently involves high manufacturing cost. Therefore, there is a strong demand for a new memory device that can reduce the cell area with securing a requisite volume of information without requiring complex manufacturing steps.
In attempt to meet the demand, there have been proposed a ferroelectric random access memory (FeRAM) where a capacitor thin film with ferroelectric properties such as strontium bithmuth tantalate (SBT) is used for a capacitor in place of a conventional silicon oxide film or a silicon nitride film.
In
FIG. 1
, there is shown a cross sectional view setting forth a conventional semiconductor memory device
100
for use as FeRAM, disclosed in U.S. Pat. No. 5,864,153, entitled “CAPACITOR STRUCTURE OF SEMICONDUCTOR MEMORY CELL AND FABRICATION PROCESS THEREOF”. The semiconductor memory device
100
includes an active matrix
10
incorporating a metal oxide semiconductor (MOS) transistor therein, a capacitor structure
23
formed on top of the active matrix
10
, a bit line
34
, a metal interconnection
36
and a plate line
38
.
In
FIGS. 2A
to
2
E, there are illustrated manufacturing steps involved in manufacturing a conventional semiconductor memory device
100
.
The process for manufacturing the conventional semiconductor memory device
100
begins with the preparation of an active matrix
10
having a silicon substrate
2
, a MOS transistor formed thereon as a selective transistor, an isolation region
4
and a first insulating layer
16
formed on the MOS transistor and the isolation region
4
. The first insulating layer
16
, e.g., made of boron-phosphor-silicate glass (BPSG), is formed over the entire surface by chemical vapor deposition (CVD). The MOS transistor includes a pair of diffusion regions
6
serving as a source and a drain, a gate oxide
8
, a spacer
14
and a gate line
12
.
In a subsequent step, there is formed on top of the active matrix
10
a buffer layer
18
, a first metal layer
20
, a dielectric layer
22
and a second metal layer
24
, sequentially, as shown in FIG.
2
A. The buffer layer
18
is made of titanium (Ti) and the first metal layer
20
is made of platinum (Pt). The dielectric layer
22
is made of a ferroelectric material. The buffer, the first and the second metal layers
18
,
22
,
24
are deposited with a sputter and the dielectric layer
20
is spin-on coated.
Thereafter, the second metal layer
24
and the dielectric layer
22
are patterned into a predetermined configuration. And then, the first metal layer
20
and the buffer layer
18
are patterned into a second predetermined configuration by using a photolithography method to thereby obtain a capacitor structure
23
having a buffer
18
A, a bottom electrode
20
A, a capacitor thin film
22
A and a top electrode
24
A, as shown in FIG.
2
B. The buffer layer
18
A is used for ensuring reliable adhesion between the bottom electrode
20
A and the first insulating layer
16
.
In a next step, a second insulating layer
26
, e.g., made of silicon dioxide (SiO
2
), is formed on top of the active matrix
10
and the capacitor structure
23
by using a plasma CVD, as shown in FIG.
2
C.
In an ensuing step, a first and a second openings
27
,
28
are formed in the second and the first insulating layers
26
,
16
in such a way that they are placed at positions over the diffusion regions
6
, respectively. A third and a fourth openings
30
,
32
are formed on top of the capacitor structure
23
through the second insulating layer
26
, thereby exposing portions of the bottom and the top electrodes
20
A,
24
A, respectively, as shown in FIG.
2
D.
Thereafter, an interconnection layer, e.g., made of a conducting material such as aluminum (Al), is formed over the entire surface including the interiors of the openings
27
,
28
,
30
,
32
, and is patterned to form a bit line
34
, a metal interconnection
36
and a plate line
38
, thereby obtaining the semiconductor memory device
100
, as shown in FIG.
2
E.
In case when a multi-level process (not shown) is applied to the above-described semiconductor device
100
, an intermetal dielectric (IMD) layer, e.g., made of SiO
2
, must be formed on top of the bit line
34
, the metal interconnection
36
and the plate line
38
by using a plasma CVD for the purpose of the insulation between each metal layer. Since the plasma CVD utilizes silane (SiH
4
) as a source gas, the atmosphere for forming the IMD layer becomes a hydrogen rich atmosphere, and in this step, the silicon substrate
2
is annealed at 400° C.
Therefore, the hydrogen gas generated by the plasma CVD process damages the capacitor thin film
22
A and the top electrode
24
A during the annealing process. That is, the hydrogen gas penetrates to the top electrode
24
A, further reaches to the capacitor thin film
22
A and reacts with oxygen atoms constituting the ferroelectric material of the capacitor thin film
22
A.
Furthermore, after the multi-level process, a passivation layer (not shown), e.g., made of SiO
2
, is formed thereon by using a plasma CVD. This process also has a hydrogen rich atmosphere. Therefore, the hydrogen gas generated by the passivation process also damages the capacitor structure
23
.
These problems, therefore, tend to make it difficult to obtain the desired reproducibility, reliability and yield.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor device incorporating hydrogen barrier layers therein to prevent a capacitor thin film, e.g., made of a ferroelectric material, from a hydrogen damage which is caused by a plasma chemical vapor deposition (CVD) during the formation of an inter-metal dielectric layer or a passivation layer.
It is another object of the present invention to provide a method for manufacturing a semiconductor device incorporating hydrogen barrier layers therein to prevent a capacitor thin film from a hydrogen damage which is generated by a plasma CVD during the formation of an inter-metal dielectric layer or a passivation layer.
In accordance with one aspect of the present invention, there is provided a semiconductor device for use in a memory cell, including: an active matrix provided with a semiconductor substrate, a transistor formed on the semiconductor substrate, an isolation region for isolating the transistor and a first insulating layer formed on top of the transistor and the isolation region; a capacitor structure, formed on top of the first insulating layer, composed of a bottom electrode, a capacitor thin film placed on top of the bottom electrode and a top electrode formed on top of the capacitor thin film; a second insulating layer formed on top of the transistor and the capacitor structure; a metal interconnection formed on top of the second insulating layer to electrically connect the transistor to the capacitor structure; a barrier layer formed on top of the metal connection; and an inter-metal dielectric (IMD) layer formed on top of the barrier layer by using a plasma chemical vapor deposition (CVD) in a hydrogen rich atmosphere, wherein the barrier layer is used for preventing the capacitor structure from the hydrogen.
In accordance with another aspect of the present invention, the
Yang Woo-Seok
Yeom Seung-Jin
Yu Yong-Sik
Cao Phat X.
Doan Theresa T.
Hyundai Electronics Industries Co,. Ltd.
Jacobson & Holman PLLC
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