Semiconductor device having a capacitance element with excellent

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device

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3613213, 326 68, 257905, 257907, H01L 27108, H01L 2976, H01L 2994, H01G 906

Patent

active

058014128

ABSTRACT:
N type impurity regions are formed at the surface of N well similarly to a DRAM memory cell. Electrode layers corresponding to storage nodes and conductive layers 9a and 9b corresponding to cell plates are formed for predetermined impurity regions among the impurity regions. Conductive layers are isolated from each other electrically in a DC fashion and connected to electrode nodes VA and VB, respectively. The sets of capacitors formed by a predetermined number of memory cell capacitors connected in parallel through the N well are connected in series. As a result, a capacitor with excellent area efficiency which utilizes the characteristics of the memory cell capacitor can be realized.

REFERENCES:
patent: 4879631 (1989-11-01), Johnson et al.
patent: 4980799 (1990-12-01), Tobita
patent: 5243209 (1993-09-01), Ishii
patent: 5465058 (1995-11-01), Krenik et al.

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