Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-05-11
2002-07-09
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S296000
Reexamination Certificate
active
06417557
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and in particular to a semiconductor device comprising a capacitance adjustment section for conducting adjustment of wiring capacitance in a simple and rational manner.
The present specification is based on Japanese Patent Application, Unpublished, No. Hei 11-133286 which has been submitted in Japan and the content of which is incorporated as one portion of the present specification.
2. Description of the Related Art
FIG. 6
shows a sample construction, by conventional techniques, of a DRAM (Dynamic Random Access Memory). Up to now in semiconductor devices such as DRAM, package miniaturization has progressed considerably, in order to ensure that even with the increases in chip surface area associated with increasing memory capacity, the packaging density is not lowered.
FIG. 6
shows an example of a CSP (chip size package) of a recently employed package type in which miniaturization has progressed significantly. In the CSP shown, a substrate
100
of a polyimide and a semiconductor chip
101
are fixed together with the chip surface facing the substrate and then sealed with a resin
102
. A plurality of solder balls
103
which function as external terminals are provided on the lower surface of the substrate
100
, while a plurality of pads (not shown in the figure) which function as chip wiring terminals are formed on the surface of the semiconductor chip
101
. Each solder ball
103
and each pad are then connected electrically via copper wiring (not shown in the figure) formed on the upper surface of the substrate, and conducting materials (not shown in the figure) which are imbedded in through holes which penetrate through the substrate.
FIG. 7
is a schematic diagram showing a circuit block of a semiconductor chip. The chip comprises four memory cell blocks
104
, and peripheral circuits
105
disposed about the periphery thereof. A single line of a plurality of pads
106
is formed in the center of the chip. In the figure, the wiring connected to the pads
106
has been omitted.
FIG. 8
shows the aforementioned DRAM viewed from beneath (from the solder ball side). In this example DRAM, the solder balls
103
on the substrate
100
are disposed in three lines on each of the left and right hand sides, while the pads
106
on the semiconductor chip
101
are disposed in a centrally positioned single line. Consequently, the wiring
107
for connecting each of the solder balls
103
and each of the pads
106
, cannot be wired in a straight line, and must be suitably managed so as to avoid short circuits with other wiring
107
. Moreover in
FIG. 8
only a portion of the wiring
107
for connecting the solder balls
103
and the pads
106
is shown, although the remaining portions are wired in a similar manner.
However, as is evident from
FIG. 8
, because the length of each section of wiring
107
differs, the wiring capacitance of each section of wiring
107
will also differ. That is, the wiring capacitance from the external terminal of the DRAM to the pad will vary between pins, and left as is, there is a danger that the signal timing during the operations for the reading and writing of data will vary between pins, resulting in an error. Consequently, in this type of semiconductor chip, a capacitance adjustment section is usually provided for matching the wiring capacitance of each section of wiring.
FIG. 9
is a diagram showing the construction of a capacitance adjustment section of the aforementioned DRAM. The capacitance adjustment section
108
is basically constructed according to gate capacitance. That is, a capacitance is formed from a diffusion layer
109
formed on the surface of the semiconductor substrate, and gate electrodes
110
a,
110
b,
110
c,
and
110
d
which oppose the diffusion layer
109
via a gate insulating film. Furthermore, the plurality (four in the example shown) of gate electrodes
110
a,
110
b,
110
c,
110
d
are provided for adjusting the capacitance value to various values, and each gate electrode
110
a,
110
b,
110
c,
110
d
is connected to a first aluminum wiring
112
via a through hole
111
. Each of the first aluminum sections of wiring
112
are connected respectively to a second aluminum wiring
114
via a through hole
113
. Each of the second aluminum sections of wiring
114
is then connected to an input signal line
116
connected to an input pad
115
.
Moreover in the present specification, “first aluminum wiring” refers to the first layer side (the lower layer) of aluminum wiring of a double layer wiring construction, whereas “second aluminum wiring” refers to the second layer side (the upper layer) of aluminum wiring.
The gate length of each of the aforementioned four gate electrodes
110
a,
110
b,
110
c
and
110
d
is different, and referenced against the shortest gate length, the other gate lengths are set to values twice, three times, and four times as long respectively. Correspondingly, the capacitance values when referenced against the capacitance of the shortest gate length are twice, three times, and four times as large respectively. That is, the capacitance values are set so that the sequence of values from the shortest gate length to the longest gate length are, for example, 10fF (femtoFarad), 20fF, 30fF, and 40fF respectively.
In a DRAM provided with this type of capacitance adjustment section
108
, the matching of wiring capacitance is conducted by assembling the semiconductor chip into a packaged state, and following measurement and evaluation of the electrical characteristics of the package, using the evaluation results to determine the input signal wiring sections which require additional capacitance to match the largest observed wiring capacitance, and then using the capacitance adjustment section
108
to add the necessary capacitance. In the case where capacitance is actually to be added, the value of the capacitance being added is altered by making a design change to the mask pattern of the second aluminum wiring, and connecting a gate capacitance with one of the four aforementioned capacitance values to the input signal wiring. Consequently, in the case of the example described above, by suitable combinations of the four different gate capacitances, capacitance additions of between 10fF and 100fF in increments of 10fF are possible.
However, the following problems arise with the conventional DRAM wiring capacitance adjustment methods described above.
Conducting adjustments of the wiring capacitance by combining gate capacitances for which the capacitance values are fixed, means that adjustments can only be made for limited increments (10fF in the case of the above example) and up to a limited upper limit (100fF in the case of the above example), and so fine adjustments in the capacitance value are difficult to achieve. Provision of a plurality of gate capacitances incorporating smaller capacitance values can be seen as a way of alleviating this problem, but in such cases the increase in the number of gate capacitances increases the surface area occupied by the capacitance adjustment section, resulting in an undesirable increase in the surface area of the chip. Furthermore, addition of each new gate capacitance requires a design change in the mask pattern of the lower layer, meaning the time and effort required for mask design changes increases undesirably.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device comprising a capacitance adjustment section which enables the free setting of the amount of adjustment of a wiring capacitance and for which the adjustment operation can be carried out simply.
In order to achieve the above object, a semiconductor device of the present invention comprises the following two methods.
First, a first semiconductor device according to the present invention comprises a capacitance adjustment section for adjusting wiring capacitance, and the capacitance adjustment section further comprises a capacitance adjustment w
NEC Corporation
Ngo Ngan V.
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