Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-02-28
2006-02-28
Tran, Michael (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S230030
Reexamination Certificate
active
07006381
ABSTRACT:
The invention relates to a semiconductor device having a byte-erasable EEPROM memory comprising a matrix of rows and columns of memory cells. In order to provide a semiconductor device having a byte-erasable EEPROM which has a reduced chip size and increased density and which is suitable for low-power applications it is proposed according to the present invention that the memory cells each comprise a selection transistor having a selection gate and, arranged in series therewith, a memory transistor having a floating gate and a control gate, the selection transistor being further connected to a source line of the byte-erasable EEPROM memory, which source line is common for a plurality of memory cells, and the memory transistor being further connected to a bit line of the byte-erasable EEPROM memory, wherein the columns of memory cells are located in separate p-type wells separated by n-type wells. Preferably, high voltage switching elements are provided for dividing global control gates into local control gates for each column of bytes.
REFERENCES:
patent: 5406521 (1995-04-01), Hara
patent: 5455790 (1995-10-01), Hart et al.
patent: 6038170 (2000-03-01), Shiba
patent: 6475846 (2002-11-01), Marotta et al.
patent: 2000 021183 (2000-01-01), None
patent: WO 00 75994 (2000-12-01), None
Patent Abstracts of Japan vol. 2000, No. 04, Aug. 31, 2000 & JP 2000 021183, Jan. 21, 2000, Abstract; Figures 1, 3-6.
Dormans Guido Jozef Maria
Garbe Joachim Christoph Hans
Verhaar Robertus Dominicus Joseph
Tran Michael
Zawilski Peter
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