Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – With base region having specified doping concentration...
Patent
1997-06-09
1998-05-12
Jackson, Jerome
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
With base region having specified doping concentration...
257593, 257577, 257565, 257378, H01L 27082
Patent
active
057510539
ABSTRACT:
A bipolar transistor, an nMOS transistor and pMOS transistor are formed at a main surface of a p-type semiconductor substrate. The bipolar transistor includes a collector layer, a base layer and an emitter layer. Collector layer located immediately under base layer contains impurity of n-type at a concentration not more than 5xl0.sup.18 cm.sup.-3. Base layer located immediately under emitter layer has a diffusion depth not more than 0.3 .mu.m. A semiconductor device including the bipolar transistor having the above structure is used in a circuit performing small amplitude operation. Thereby, it is possible to provide the semiconductor device having the bipolar transistor, which can be manufactured at a low cost and can operate at a high speed.
REFERENCES:
patent: 5336926 (1994-08-01), Matthews
Paul R. Gray and Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Second Edition, Chapters 2.3-2.4.
"High Performance 1.0UM N-Well CMOS/Bipolar Technology", H. Momose et al., Symposium of VLSI Technology, Sep. 1983, pp. 40-41.
"A 1.0UM N-Well CMOS Bipolar Technology for VLSI Circuits", J. Miyamoto et al., IEDM DIgest of Technical Papers, Dec. 1983, pp. 63-66.
"High Speed BICMOS VLSI Technology With Buried Twin Well Structure", A. Watanabe et al., IEDM Digest of Technology Papers, 1985, pp. 423-426.
Jackson Jerome
Kelley Nathan K.
Mitsubishi Denki & Kabushiki Kaisha
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