Radiation imagery chemistry: process – composition – or product th – Including control feature responsive to a test or measurement
Reexamination Certificate
1999-07-07
2001-02-06
Young, Christopher G. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Including control feature responsive to a test or measurement
C430S311000
Reexamination Certificate
active
06183920
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device geometrical pattern correction process for making advance changes, in a mask geometrical pattern for use in the manufacture of semiconductor devices or the like in order to obtain a transferred image that is close to a desired design pattern. The invention also relates to a semiconductor device manufacturing process and a geometrical pattern extraction process adapted for use in the above correction process.
2. Prior Art
Current techniques for manufacturing semiconductor devices and the like essentially require a photographic step in which a mask geometrical pattern for semiconductor devices is transferred to a resist material on a semiconductor substrate by use of an exposure light source.
In recent years, miniaturization in semiconductor device manufacturing processes is advancing at a pace faster than that of reduction in the wavelengths of exposure light sources. This has brought about a strong need for a photographic step in which transferring is carried out with a pattern having a size equivalent to or less than the wavelength of an exposure light source. As a result, there often arises the problem of the difference between a geometrical pattern obtained after transferring and its associated mask geometrical pattern initially designed.
One of the causes of such a difference in pattern is “corner rounding” which causes, after transferring, depressions in irregular geometry designed as a mask geometrical pattern. If a depression occurs in a convex gate portion of a transistor or in a concave diffusion layer portion which receives the projection of a gate, a desired amount of projection of the gate from the diffusion layer can be no longer ensured. This leads to electrical continuity between the source and drain of the transistor, resulting in increases in the current of the power source and even a failure in operation in the worst case, where a semiconductor device formed from such a pattern is used. As a matter of course, it is necessary to devise a measure to prevent such problematic depressions in semiconductor devices.
With reference to the accompanying drawings, there will be explained one attempt that has been previously made to eliminate the adverse effect of corner rounding on the projection amount of a gate.
FIGS. 21 and 22
show one example in which no measure is taken to ensure a satisfactory gate projection amount.
In the mask geometrical pattern shown in
FIG. 21
, a transistor gate
511
projects from a diffusion layer
513
. In this pattern, a measure to compensate for a decrease in the projection amount of the gate is not taken, and therefore another pattern
512
can be made. However, the gate of the mask geometrical pattern shown in
FIG. 22
obtained after transferring stands back because of corner rounding so that the source and drain of the diffusion layer are short-circuited.
FIGS. 23 and 24
show one example of conventional techniques for preventing a decrease in the projection amount of a gate.
According to the conventional technique depicted in
FIG. 23
, a portion which is likely to decrease in projection amount after transferring because of corner rounding is detected at the stage of designing a mask geometrical pattern and the mask geometrical pattern is modified to compensate for possible decreases. Therefore, the mask geometrical pattern obtained after transferring has an appropriate gate projection amount in spite of a depression in the gate atributable owing to corner rounding.
The above conventional technique, however, reveals the problem that since the projection amount of the gate in the mask geometrical pattern is increased, there is no space to accommodate another pattern
512
because of the occupation of the increased gate portion. More specifically, the mask geometrical pattern shown in
FIG. 23
which has been modified to compensate for a decrease in gate projection amount does not have a space for the placement of the pattern
512
, while the mask geometrical pattern shown in
FIG. 21
which has not undergone such modification can include the pattern
512
. This is a disadvantage to the conventional technique in view of effective space utilization and reduction in chip area.
The area of chips is the most critical factor in determining the cost of chips as well as in developing economically competitive chips.
The present invention is directed to overcoming the above problems presented by the prior art and one of the objects of the invention is therefore to provide a semiconductor device geometrical pattern correction process, semiconductor device manufacturing process and geometrical pattern extraction process, which are capable of compensating for a decrease in the projection amount of a gate due to corner rounding which accompanies miniaturization, while avoiding increased chip area.
SUMMARY OF THE INVENTION
According to the invention, there is provided a semiconductor device geometrical pattern correction process comprising the steps of:
detecting a concave diffusion layer corresponding portion; and
correcting at least either the concave diffusion layer corresponding portion or a transistor gate corresponding portion which projects from the concave diffusion layer corresponding portion in order to ensure the projection of a gate from the concave diffusion layer corresponding portion against possible corner rounding.
The semiconductor device geometrical pattern correction process of the invention is arranged such that, with a view to compensating for a decrease in the projection amount of a gate owing to corner rounding, modification of the diffusion layer by reduction or modification of the transistor gate by enlargement is made in the transistor gate corresponding portion which projects from the concave diffusion layer corresponding portion on the semiconductor device mask geometrical pattern, so that gate depression with a decreased projection amount owing to corner rounding induced after the photographic step can be compensated.
In accomplishing the above primary object, the invention does not cause increased chip area, which is a problem presented by conventional techniques, so that the invention can thus contribute to the development of competitive chips. In addition, since the measure is focused on the compensation for a decrease in the projection amount of the gate, the amount of data that accompany the measure can be minimized and mask fabrication problems can be eliminated.
In the above arrangement, the step of correcting the concave diffusion layer corresponding portion is designed to make correction by reduction of the base of the concave portion and may include the step of performing geometrical pattern logical operation.
The step of correcting the concave diffusion layer corresponding portion is designed to make correction by reduction of the base of the concave portion and reduction of regions of sides which respectively contact the base in the concave portion, the regions being in the vicinity of the ends of the base. This step may include the steps of correcting a geometrical pattern and performing geometrical pattern logical operation.
The step of correcting the transistor gate projecting from the concave diffusion layer corresponding portion is designed to make correction by enlargement of regions of sides which respectively contact an end line in the transistor gate, the regions being positioned in the vicinity of both ends of the end line. This step may include the steps of measuring the difference between two geometrical patterns, correcting a geometrical pattern and performing geometrical pattern logical operation.
The step of correcting a transistor gate corresponding portion projecting from the concave diffusion layer corresponding portion is designed to make correction by enlargement of an end line of the transistor gate corresponding portion and enlargement of regions of sides which respectively contact the end line in the transistor gate corresponding portion, the regions being positioned in th
Mukai Kiyohito
Shibata Hidenori
Tsujikawa Hiroyuki
Matsushita Electric - Industrial Co., Ltd.
Stevens Davis Miller & Mosher L.L.P.
Young Christopher G.
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