Semiconductor device gate-drain configuration

Details Semiconductor device gate-drain configuration Semiconductor device gate-drain configuration

1979-08-10

1981-11-10

Wojciechowicz, Edward J.

357 22, 357 52, 357 55, 357 90, H01L 2948

Patent

active

043001483

ABSTRACT:
Power handling capability and gain of metal-semiconductor field effect devices is adversely affected by a phenomenon variously known as gate-drain avalanche or gate breakdown which occurs at elevated gate-drain voltage. Consequently, it is desirable to design devices so as to maximize gate-drain breakdown voltage V.sub.gd consistent with maximum output power capability.
According to the invention, such voltage is maximized by a gate-drain configuration which involves approximate equalization of per-unit-area mobile charge in a portion of the active layer under the gate contact and in an adjoining portion between gate and drain contacts. Equalization of charge may be achieved by appropriate doping or appropriate choice of layer thickness, either alone or in combination. In particular, if dopant concentration per unit volume is essentially equal in the two portions, approximate equalization of conducting channel thickness in the two portions is called for. Devices of the invention are capable of higher gain and output power as is desirable in applications such as, e.g., the amplification of microwaves.

REFERENCES:
patent: 3767984 (1973-10-01), Shinoda et al.
IEEE Trans. Elec. Dev.-vol.-ED-23, No. 4, Apr. 1976, pp. 388-394, Fukuta et al.
IEEE Trans. on Microwave Theory & Tech.-vol. MTT-27, No. 5, May 1979, Di Lorenzo et al., pp. 367-378.
IEDM Tech. Digest., Dec. 1978, pp.364-367, Eastman.
Wiley, Interscience, 1969, p. 411, SZE.
Bell Lab. Record, Sep. 1978, pp. 209-215, Di Lorenzo et al.
IEEE Trans. on Microwave Theory & Tech.-vol. MTT-24, Jun. 1976, Fukuta et al., pp. 312-317.
Inst. Phys. Conf., Ser. No. 33B, 1977, pp. 262-270, Wemple et al.

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