Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-11-27
2003-03-11
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S665000, C257S910000, C102S202400, C361S275100, C438S132000, C438S215000, C438S281000
Reexamination Certificate
active
06531757
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device with a fuse box and a method of manufacturing the same and, in particular, to a semiconductor device with a fuse box having a fuse member consisting of a metal which can be cut by a laser beam and a method of manufacturing the same.
2. Description of the Background Art
Generally, in a semiconductor storage device such as a DRAM (Dynamic Random Access Memory), a fuse member is arranged on a circuit for replacing a redundant circuit for compensating for a defect of a memory cell generated by manufacturing steps or the like. The fuse member arranged in the circuit of the memory cell in which the defect is detected is cut by a laser beam or the like to replace the memory cell with the redundant circuit. In addition, the fuse member may be arranged to adjust an internal voltage in the circuit.
The fuse members, in general, are binded and arranged in one fuse box with respect to the management of the fuse members. For example, the fuse box, as shown in
FIG. 17
, has a plurality of fuse members for electrically connecting gate electrodes formed on an oxide film
13
for element isolation. As the oxide film
13
for element isolation, a LOCOS or a trench is generally used. In order to arrange a fuse box on the oxide film
13
, a trench having a flat upper portion, in particular, shallow trench isolation (STI) is most generally used. However, further flattening is necessary, and advanced flattening by a CMP (Chemical Mechanical Polishing) method is performed. At present, an improvement in technique for the CMP process is advanced.
When an element isolation oxide film is flattened by improving the CMP process, a large dishing (that is dented shape) may be generated in a large-area element isolation oxide film. The large dishing is considered to be generated by a compressional difference between portions of an isolation pattern. When a fuse box is laid out on a large isolation pattern, as shown in the sectional view of
FIG. 18
, a large dishing may be generated on the large isolation pattern. Since the central portion of the large isolation pattern is dished with respect to the end portion, of a large number of fuse members arranged on the isolation pattern, fuse members arranged at the central portion and fuse members arranged at the end portion are different in level. For this reason, when the fuse members are to be cut by a laser beam focused on a predetermined focal point, the laser beam cannot be precisely focused on the fuse members having different levels. Therefore, the fuse members may be unreliably cut.
On the other hand, when a large dishing is generated in an oxide film, the oxide film falls at the end portion of the isolation pattern to expose the edge portion of the silicon substrate. When a gate oxide film and a gate electrode are formed on the oxide film in this order, it is known that the gate oxide film has the thickness at the edge portion smaller than the thickness at the other portion. In this gate insulating film, insulating breakdown may occur because dielectric strength is degraded at a portion where the thickness is small around the edge portion. The thickness of the gate oxide film is reduced with micropatterning of a wiring layer or the like. The reduction in thickness at the edge portion is advanced, and occurrence of insulating breakdown become serious.
SUMMARY OF THE INVENTION
Therefore, it is the first object of the present invention to provide a semiconductor device having a fuse box in which a fuse member for electrically connecting gate electrodes formed on an element isolation oxide film has no difference in level. It is the second object of the present invention to provide a semiconductor device having a stable fuse box which is formed on an element isolation oxide film and in which insulating breakdown does not occur in a wiring gate electrode of a fuse member.
In accordance with one aspect of the present invention, there is provided a semiconductor device with a fuse box that includes at least two gate electrodes and a fuse member. The two gate electrodes are formed on at least one insulating film on a semiconductor substrate. The fuse member is formed on the insulating film on the semiconductor substrate. Therefore, the two gate electrodes are electrically connected to each other by the fuse member. In addition, the insulating film and a field region are constituted by a semiconductor region. They are arranged adjacent to each other in a frame-like guard ring, which is constituted by a semiconductor region that is formed on the semiconductor substrate.
In another aspect of the present invention, there is provided a semiconductor device with a fuse box that includes at least two gate electrodes and a fuse member. The two gate electrodes are formed on at least one insulating film in a frame-like guard ring, which is constituted by a semiconductor region formed on a semiconductor. The fuse member is formed on the insulating film on the semiconductor substrate. The two gate electrodes are electrically connected to each other by the fuse member. In addition, the gate electrode is electrically connected to the outside through a connection unit arranged across the upper portion of the guard ring.
In a further aspect of the present invention, the field region is constituted by a semiconductor region formed on the semiconductor a substrate and the insulating film are arranged adjacent to each other in the fuse box.
In another aspect of the present invention, a plurality of columns in each of which the field region and the insulating film are adjacent to each other are arranged in the fuse box.
In a yet further aspect of the present invention, the two gate electrodes formed on the insulating film are electrically connected to each other, through perpendicular connection units formed on the gate electrodes in an upwardly perpendicular direction, by the fuse member extending in the horizontal direction between the end portions of the perpendicular connection units.
In a yet further aspect of the present invention, the perpendicular connection unit includes a connection unit arranged across the upper portion of the guard ring.
The present invention also provides a method of manufacturing a semiconductor device with a fuse box. The process includes the following steps.
S1: forming a mask film on a semiconductor substrate;
S2: forming a resist pattern on the semiconductor substrate;
S3: etching the semiconductor substrate to form a field region constituted by a semiconductor region;
S4: removing the resist pattern;
S5: etching the semiconductor substrate by using the mask film to form a trench;
S6: burying the trench with an insulating film;
S7: flattening the insulating film;
S8: forming a gate electrode on the insulating film; and
S9: arranging a fuse member for electrically connecting the gate electrode.
Then the resist pattern is constituted by a pattern in which the trench and the field region are arranged adjacent to each other on the semiconductor substrate by the step of etching the semiconductor substrate such that the field region is formed.
In another aspect of the present invention, the gate electrode is formed on the inside of a guard ring serving as an outer edge portion of the fuse box in the step of forming the gate electrode. In addition, a connection unit, which is connected between the electrode and the fuse member, is formed across the upper portion of the guard ring to connect to the outside in the step of arranging the fuse member.
In a yet further aspect of the present invention, the resist pattern includes a plurality of columns of patterns in each of which the trench and the field region are arranged adjacent to each other on the semiconductor substrate by the step of etching the semiconductor substrate such that the field region is formed.
According to the semiconductor device with the fuse box of the present invention, a field region constituted by a semiconductor region and an insulating film are arranged adjacent to each oth
Flynn Nathan J.
Wilson Scott R
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