Stock material or miscellaneous articles – Structurally defined web or sheet – Discontinuous or differential coating – impregnation or bond
Reexamination Certificate
2001-04-24
2002-04-30
Jones, Deborah (Department: 1775)
Stock material or miscellaneous articles
Structurally defined web or sheet
Discontinuous or differential coating, impregnation or bond
C428S210000, C428S426000, C428S428000, C428S432000, C428S446000, C428S450000, C257S622000
Reexamination Certificate
active
06379782
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to techniques by which metal wiring, plugs, pads, etc. are formed on a semiconductor wafer through chemical mechanical polishing (hereinbelow, suitably termed “CMP”).
2. Description of the Related Art
In recent years, various microfabrication technologies have been researched and developed with the higher integration densities and finer structures of semiconductor devices. Among them, CMP technology is indispensable in cases of forming embedded metal wiring, interlayer connection plugs, etc.
Now, a prior-art process for forming damascened copper wiring by CMP will be explained with reference to the drawings.
Initially, as shown in
FIGS. 1A-1C
, a copper film
6
is formed on a silicon oxide film
4
formed with a wiring groove pattern.
More specifically, first of all, a silicon oxide film
2
, a silicon oxynitride film
3
and the silicon oxide film
4
are formed on a silicon wafer
1
in the mentioned order. Secondly, wiring grooves in the predetermined pattern are formed by known lithographic and etching techniques. On this occasion, the silicon oxide film
4
on the peripheral part of the wafer is removed by performing a peripheral exposure with the remaining part of the wafer being masked. The peripheral exposure is a process for removing a resist which remains in the vicinity of the peripheral part of the wafer. Point A is an inner end position of the peripheral exposure. Owing to the peripheral exposure, it is possible to prevent a semiconductor manufacturing apparatus from being contaminated by the remaining resist, the peeled part of the silicon oxide film
4
on the peripheral part of the wafer, and so forth.
Subsequently, a barrier metal film
5
is formed on the whole surface of the wafer by sputtering, whereafter the copper film
6
is formed. The copper film
6
is formed by plating, CVD (Chemical Vapor Deposition), or the like. When the formation of the copper film
6
has ended, copper adheres to the back surface and peripheral part of the silicon wafer
1
as shown in
FIG. 1B and 1C
. Accordingly, the copper adhering to these parts is removed by wet processing (refer to FIGS.
2
A-
2
C). More specifically, the adhesion between the barrier metal film
5
and the copper film
6
is not sufficient so that, when an interlayer insulating film is formed without removing the adhering copper, the copper film
6
peels off to incur the contamination of the wafer and the apparatus (termed “cross-contamination” below) through the conveyance system. Moreover, the copper having once peeled off adheres to the silicon wafer
1
again to cause an inferior film formation or adversely affect a device performance by diffusing into the silicon wafer
1
.
In order to avoid such problems, the copper on a peripheral exposure region needs to be completely removed as shown in FIG.
2
C. Therefore, a region where the copper film
6
is etched and removed is set so as to extend from a position inside the peripheral exposure region (nearer to the central part of the wafer) to the peripheral edge of the silicon wafer
1
, that is, from a position at which the patterned silicon oxide film
4
exists, to the peripheral edge of the silicon wafer
1
(refer to FIGS.
2
A-
2
C). In this way, the copper on the peripheral exposure region can be reliably removed. Point B is an inner end position of wet etching for removal of copper at a peripheral region and back surface of the wafer. C is a region of exposed wiring grooves. D is a region of peripheral exposure.
Subsequently, the superfluous parts of the copper film
6
and barrier metal film
5
are polished away by the CMP, thereby to form the damascened copper wiring in which the copper film
6
is embedded in the wiring grooves (refer to FIGS.
3
A-
3
C). The CMP is implemented in such a way that the surface of the copper film
6
is polished with a polishing slurry by a polishing pad. The polishing slurry usually contains polishing grains and an oxidizer as main components. When the copper film
6
is polished by the CMP, polishing debris
8
(chiefly, polishing grains) having appeared due to the CMP inevitably adhere into the wiring grooves vicinal to the peripheral edge of the silicon wafer
1
. As shown in
FIG. 3C
, therefore, the wiring grooves are filled with the polishing debris
8
in the vicinity of the peripheral edge of the wafer
1
.
Thereafter, a protective film
9
and the interlayer insulating film
10
which are made of SiN are formed on the whole surface of the wafer, whereby the damascened copper wiring is finished up (refer to FIGS.
4
A-
4
C).
However, the copper wiring formed as explained above is in the state in which the polishing debris
8
are packed into the wiring grooves vicinal to the peripheral edge of the wafer as shown in
FIGS. 4A-4C
, and it is liable to pose various problems, for example, that the interlayer insulating film
10
peels off on the polishing debris
8
. For the purpose of avoiding such problems, it is also considered to remove the polishing debris
8
at the stage of
FIGS. 3A-3C
. It is difficult, however, to sufficiently remove the polishing debris
8
adhering in the grooves. At a region E, an innerlayer film might peel off. Point B′
0
is an inner end position of wet etching for removal of copper residue like a sidewall.
Meanwhile, in recent years, a low permittivity film of HSQ (Hydrogen Silisesquioxane) or the like is often employed instead of the silicon oxide film
4
as the material of an insulating film for wiring layers in order to prevent the crosstalk between adjacent wiring lines, etc. In general, however, the low permittivity film is less resistant against chemicals and is susceptible to damages during a manufacturing process. Therefore, when the HSQ film is substituted for the silicon oxide film
4
in the process of FIG.
1
A-
FIG. 4C
, it is damaged by an etchant at the stage of
FIGS. 2A-2C
. This state is shown in
FIGS. 5A-5C
. As seen from these figures, the wiring grooves are exposed in the vicinity of the peripheral edge of the wafer. Inside of each wiring groove is covered with the barrier metal film
5
. Nevertheless, the barrier metal film
5
is not entirely uniform in thickness to cover the wiring groove completely, but it includes a local thinner part and even fails to cover the wiring line. Therefore, the etchant permeates through such parts at the wet etching step of the copper, resulting in the damages of the low permittivity film
15
. Thus, voids appear in the HSQ film
15
to incur such various problems that the interlayer insulating film
10
above the voids peels off and that the permittivity characteristics of the low permittivity film
15
degrade. At a region F, a low permittivity film is damaged.
SUMMARY OF THE INVENTION
In view of the above circumstances, an object of the present invention is to prevent wiring grooves from being filled with polishing debris of CMP and to prevent a wiring-layer insulating film from suffering damage in the vicinity of the peripheral edge of a wafer, thereby to prevent the interlayer insulating film from peeling off and to improve the product yield and the reliability of a semiconductor device.
With a method of manufacturing a semiconductor device according to the present invention, at least one insulating layer is first formed on the whole surface of a wafer. Secondly, a plurality of recesses is formed in the insulating layer. Further, a part of the insulating layer is removed on a region whose distance from the peripheral edge of the wafer is a predetermined value x or less (FIG.
7
I). Subsequently, a conductive film is formed on the whole surface of the wafer. Besides, a part of the conductive film is removed on a region whose distance from the peripheral edge of the wafer is a predetermined value y (y<x) or less (FIG.
8
C). Further, the part of the conductive film on a region except the recesses is removed by chemical mechanical polishing. Also, a part of the conductive film is removed on a region whose distance from the
Iguchi Manabu
Matsubara Yoshihisa
Takewaki Toshiyuki
Jones Deborah
NEC Corporation
Rosenman & Colin LLP
Stein Stephen
LandOfFree
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