Semiconductor device manufacturing: process – Making regenerative-type switching device – Having field effect structure
Reexamination Certificate
2001-02-15
2003-02-25
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Making regenerative-type switching device
Having field effect structure
C438S137000, C438S268000, C438S273000, C438S309000, C438S311000, C438S331000, C257S135000, C257S328000, C257S368000, C257S370000, C257S392000
Reexamination Certificate
active
06524894
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-038469, filed Feb. 16, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device for use in a power-switching device such as an insulated gate bipolar transistor (IGBT) and a power MOSFET and a method of manufacturing the same.
A semiconductor device having a punch-through structure (referred to as a PT structure hereinafter) is generally used in a power-switching device. If the power-switching device is an IGBT, the PT structure causes an N
−
layer to be completely depleted when the highest voltage is applied to the IGBT.
FIG. 12
exemplifies an IGBT having a PT structure. As
FIG. 12
shows, a P
−
-type diffusion layer
42
is formed on the surface of an N
−
layer
41
formed by epitaxial growth (hereinafter referred to as an N
−
epi-wafer), and an N
+
-type diffusion layer
43
and a P
+
-type diffusion layer
44
are formed on the layer
42
. A gate electrode
47
is formed in the N
−
epi-wafer
41
with a gate insulation film
46
interposed therebetween, and an emitter electrode
61
is selectively formed above the N
−
epi-wafer
41
. Furthermore, an N
+
-type buffer layer
62
(referred to as an N
+
buffer layer hereinafter) is formed on the underside of the N
−
epi-wafer
41
, and a P
+
-type anode layer
63
(referred to as a P
+
anode layer hereinafter) is formed on the underside of the layer
62
. A collector electrode
64
is also formed on the underside of the P
+
anode layer
63
. If the IGBT is a product having a withstanding voltage of 1200V, the thickness of the N
−
epi-wafer
41
is 100 &mgr;m, that of the N
+
buffer layer
62
is 5 &mgr;m, and that of the P
+
anode layer
63
is 400 &mgr;m.
In the IGBT having such a PT structure, a depletion layer grows from the P
−
-type diffusion layer
42
to the N
−
epi-wafer
41
when a switch is off. The N
+
buffer layer
62
suppresses the growth of the depletion layer and prevents the depletion layer from contacting the P
+
anode layer
63
.
Since the IGBT includes the P
+
anode layer
63
, a number of holes are implanted into the N
−
epi-wafer
41
from the P
+
anode layer
63
, thereby increasing an energy loss when the switch is off (referred to as Eoff hereinafter). In order to reduce the Eoff, the N
+
buffer layer
62
having a thickness of 5 &mgr;m or more is provided, and an electron beam and a photon radiation are emitted to cause crystal defects.
However, a wafer used in the PT structure corresponds to the N
−
epi-wafer
41
that grows epitaxially. The IGBT having a PT structure therefore has the problem that the manufacturing cost of the wafer is high.
A Raw wafer, which is not processed, can be considered to be an inexpensive wafer used in place of the epi-wafer
41
, and an IGBT having a non-punch-through structure (referred to as an NPT structure hereinafter) using the Raw wafer is realized. The NPT structure causes an N
−
layer to be depleted only 70% to 80% when the highest voltage is applied to the IGBT, unlike the PT structure.
FIG. 13
exemplifies an IGBT having an NPT structure. In
FIG. 13
, the same constituting elements as those of the IGBT having a PT structure shown in
FIG. 12
are indicated by the same reference numerals.
In the NPT structure, an N
−
layer
71
is formed in place of the N
−
epi-wafer
41
and the N
+
buffer layer
62
of the PT structure. If the IGBT is a product having a withstanding voltage of 1200V, the thickness of the N
−
layer
71
is 200 &mgr;m and that of the P
+
anode layer
63
is 400 &mgr;m. In the IGBT shown in
FIG. 13
, the constituents other than the N
−
layer
71
are the same as those of the IGBT shown in FIG.
12
and thus their descriptions are omitted.
In the IGBT having an NPT structure, the N
−
layer
71
should be formed up to such a desired thickness as to prevent a depletion layer, which expands when the highest voltage is applied to the IGBT, from reaching a collector electrode
64
. More specifically, if the IGBT is a product having a withstanding voltage of 1200V, the thickness of the N
−
layer
71
should be 200 &mgr;m to obtain a cutoff voltage when a switch is off, whereas in the PT structure the thickness of the N
−
epi-wafer
41
has only to be about 100 &mgr;m. In other words, the NPT structure necessitates an N
−
layer which is twice as thick as that of the PT structure in order to create the same withstanding voltage. The NPT structure therefore has the problem that power consumption increases more greatly than that in the PT structure when a switch is on.
One therefore requires that an IGBT (not shown) having a PT structure using a Raw wafer be realized and, in other words, one requires an IGBT in which an N
+
buffer layer and a P
+
anode layer are formed on the underside of a Raw wafer. The PT structure using a Raw wafer decreases a manufacturing cost and produces a device that can suppress power consumption more greatly than that having an NPT structure. The N
+
buffer layer should be formed up to such a thickness that a depletion layer is stopped from reaching an anode layer by a reverse withstanding voltage to create a device withstanding voltage and reduce the Eoff.
In the IGBT having a PT structure using a Raw wafer, however, a surface structure (a P
+
-type diffusion layer, etc.) of the wafer is difficult to form after the wafer is thinned. Thus, after the surface structure of the wafer is formed, the wafer is thinned and then the underside structure (an N
+
buffer layer, etc.) is formed by ion implantation, annealing and the like. Taking into consideration that heat damage is caused to the surface of the wafer, there is a limit to diffusion temperatures. In other words, it was difficult to form an N
+
buffer layer having a thickness (e.g., 5 &mgr;m or more) necessary for generating a device withstanding voltage and reducing the Eoff. It has been therefore thought that an IGBT having a PT structure using a Raw wafer is difficult to achieve.
As described above, the IGBT having a PT structure using an epi-wafer has the problem that the epi-wafer increases in manufacturing cost. The IGBT having an NPT structure using a Raw wafer has the problem that power consumption increases when a switch is on.
Furthermore, the IGBT having a PT structure using a Raw wafer, which is proposed to overcome the above problems, has the problem that an N
+
buffer layer having a desired thickness is difficult to form because heat damage is caused to the surface and restricts the formation of an underside structure.
Consequently, it is difficult to form an IGBT capable of reducing in manufacturing cost and suppressing power consumption.
BRIEF SUMMARY OF THE INVENTION
The present invention has been developed in order to resolve the above problems and its object is to provide a semiconductor device capable of reducing manufacturing costs and suppressing power consumption and a method of manufacturing the same.
To attain the above object, the present invention has the following structures:
A first semiconductor device of the present invention comprises a first diffusion region of a second conductivity type formed on a surface of a semiconductor substrate of a first conductivity type, a second diffusion region of the first conductivity type selectively formed on a surface of the first diffusion region, a gate electrode formed in or on the semiconductor substrate with a gate insulation film interposed therebetween, an emitter electrode electrically insulated from the gate electrode and selectively formed on the semiconductor substrate, an inactive region of the first conductivity type formed on an underside of the semiconductor substrat
Baba Yoshiro
Kobayashi Motoshige
Nozaki Hideki
Fahmy Wael
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Lee Hsien-Ming
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