Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1996-08-29
2001-12-25
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S530000, C327S535000, C365S189070, C365S189090, C323S223000
Reexamination Certificate
active
06333668
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device for creating a voltage-down (and/or booster) potential by using an internal voltage-down (and/or booster) converter with respect to an external power supply and applying the potential as an internal power supply voltage to a chip internal circuit, and more particularly to a semiconductor device capable of suppressing the current peak flowing into or from the external power supply.
2. Description of the Related Art
With the development of the fine patterning technique of semiconductor, chips such as large-scale and high-speed 32 bit- or 64 bit-MPUs containing several millions of transistors and large-capacity 16 Mbit-DRAM, 64 Mbit-DRAMs or the like are mass-produced. Therefore, the number of transistors used rapidly increases and a current consumed in the chip is extremely increased even though the power supply voltage Vcc is lowered from 5 V to 3.3 V or 3 V. An increase in the current consumption causes a serious problem of generation of power supply noise.
Particularly, if chips having a large peak current are operated at the same time, the power supply is required to have a large current supplying ability and it is necessary to dispose a large number of capacitors for stabilizing the power supply voltage on a PCB (Printed Circuit Board). Therefore, a large area for formation of capacitors is required.
Recently, in order to reduce the current consumption (power consumption) and enhance the reliability of the device, various methods for creating an internal voltage-down potential (V
int
) which is lower than the power supply voltage (V
cc
) in the chip by use of a DRAM or CPU and applying the internal voltage-down potential to the chip internal circuit have been proposed. One example of a chip containing a conventional voltage-down circuit is shown in
FIG. 1. A
voltage-down circuit
2
for lowering V
cc
to V
int
by use of a transistor Q and an operational amplifier OP is connected in series with an internal circuit
1
.
Generally, when the voltage-down circuit is not used, the power P is set to P=CV
2
f if the power supply voltage is V
cc
, the chip charging/discharging capacitance is C, and the clock frequency is f. If the internal power supply voltage is set to V
int
(<V
cc
) when the voltage-down circuit is used, the power is set to P=(V
int
/V
cc
)CV
2
f and is reduced even if the external power supply voltage is kept at V
cc
.
However, in order to keep V
int
at a constant voltage, it is necessary to supply a current having the same waveform as that of a current (I
ss
) flowing in the internal circuit
1
to the voltage-down circuit
2
in the circuit of FIG.
1
. That is, the current flowing in the transistor Q is set equal to I
ss
. Thus, it is necessary to set the relation of I
cc
(t)=I
ss
(t), and in this case, V
int
can be kept constant.
In the circuit of
FIG. 1
, V
int
and a reference voltage V
ref1
are used as the inputs to the operational amplifier and the output thereof is supplied to the gate of Q. In this case, if V
ref1
>V
int
, Q is turned “ON”, and if V
ref1
≦V
int
, Q is turned “OFF”, and as a result, the internal voltage V
int
is kept at the same value as the potential of V
ref1
.
In the above circuit, as shown in
FIG. 2
, a variation in the voltage is reduced in comparison with a case wherein the circuit is directly connected to the external power supply V
cc
when I
cc
=I
ss
, but a current supplied from the external power supply V
cc
flows so as to become equal to the current peak (I
cc
) caused by the operation of the internal circuit (I
ss
=I
cc
), and as a result, V
cc
, V
ss
vary and the noise influence is large. Further, when taking not only the internal portion of the chip but also the package and PCB into consideration, variations in V
cc
, V
ss
become larger and cause a serious problem since inductances occur in various portions as shown in FIG.
3
. For example, in
FIG. 3
, if the chip A has a large current peak, not only the chip A but also the chip B is influenced.
Further, the influence by the inductance is also exerted on the internal voltage-down potential V
int
of its own chip which should be kept at a constant potential. That is, a variation in consumption current causes a further variation in the power supply voltage by the parasitic inductances of inner leads and bonding wires on the PCB. A variation of higher frequency component than the response characteristic of the internal voltage-down circuit exists, thereby fluctuation in the high-frequency component of a variation in the external power supply voltage V
cc
is transmitted as fluctuation in the internal voltage-down potential, and thus the internal power supply voltage V
int
varies by the influence of the external inductance.
As described above, in the conventional chip and conventional voltage-down circuit, a large fluctuation in the power supply voltage occurs and this becomes larger as the integration density becomes higher. As a result, the power supply noise becomes larger, and in order to cope with this problem, it is necessary to use a main power supply having a larger supply ability and a larger number of stabilizing capacitors. Further, various problems such as deterioration in the operation speed and V
cc
margin occur due to the presence of noise occur. The above conventional circuit design is made for each chip so as to stabilize only the operation of the chip against the external noise and self noise.
SUMMARY OF THE INVENTION
An object of this invention is to provide a semiconductor device capable of reducing the peak of a current to be supplied to a chip, making the supply current smooth and suppressing the power supply noise on a PCB, for example.
In order to solve the above problems, the construction of this invention is made as follows.
According to the first aspect of this invention, a semiconductor device comprises a voltage-down circuit for generating an internal power supply voltage obtained by lowering an external power supply voltage in a chip; and a chip internal circuit applied with the internal power supply voltage obtained in the voltage-down circuit, wherein the voltage-down circuit includes a first circuit connected at one end to an external power supply, a second circuit connected between the other end of the first circuit and the internal circuit, for creating the internal power supply voltage, and a capacitor connected to a connection node of the first circuit and the second circuit and to a ground node of the chip internal circuit, and the capacitor is charged by the first circuit when a current flowing in the second circuit is smaller than a preset value and supplies a discharge current to the second circuit when the current flowing in the second circuit is larger than the preset value.
In the first aspect of this invention, the voltage-down circuit for lowering the external power supply voltage V
cc
to the internal voltage-down potential V
int
is constructed by the first and second circuits and the capacitor, and a “capacitor tank” formed of a capacitor is provided in the voltage-down circuit and charges of an amount corresponding to the current consumed in the internal circuit are supplied from the capacitor tank so as to prevent V
int
from being lowered (from varying) according to the consumed current. That is, the consumed current waveform (I
ss1
(t)) in the internal circuit and the waveform (I
AC
(t)) of the current flowing in the second circuit which connects the capacitor tank and the internal circuit become theoretically equal to each other. A current (I
cc
) which is ideally constant is supplied from the external power supply V
cc
to the capacitor tank via the first circuit to compensate for a lowering in the potential of the capacitor tank. At this time, if the internal current I
ss
is large (peak or the like), the relation of I
cc
<I
ss1
=I
AC
is set up, and if the internal current I
ss
is small, the relation of I
cc
>I
ss1
=I
AC
is set up so as
Kabushiki Kaisha Toshiba
Le Dinh
Le Dinh T.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
LandOfFree
Semiconductor device for suppressing current peak flowing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device for suppressing current peak flowing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device for suppressing current peak flowing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2570829