Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Fusible link or intentional destruct circuit
Reexamination Certificate
1997-12-11
2001-03-06
Kim, Jung Ho (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Fusible link or intentional destruct circuit
C327S513000, C327S530000
Reexamination Certificate
active
06198337
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device for outputting a reference voltage. More particularly, the present invention relates to a semiconductor device for outputting a temperature compensated reference voltage for use in various electronic devices, a crystal oscillator device comprising the semiconductor device and a method of producing the crystal oscillator device.
BACKGROUND OF THE INVENTION
A device for outputting a constant reference voltage is conventionally used in various electronic devices as a reference voltage output device for preventing a reduction in output voltage or, for controlling the output voltage, even if the battery supply voltage is varied. The present inventor previously proposed a semiconductor device for producing a constant reference voltage despite changes in temperature and/or battery voltage as disclosed in U.S. Pat. No. 4,417,263.
The semiconductor device has the circuit shown in
FIG. 5
, wherein terminal
5
provides a constant voltage output at all times. N type MOS transistors
1
and
2
are connected in series. The N type MOS transistor
1
is a depletion type MOS transistor having a gate electrode
3
and a source electrode
4
which are connected together, and a P type substrate and a source electrode which are connected together. On the other hand, the N type MOS transistor
2
is an enhancement type MOS transistor having a gate electrode
6
and a drain electrode which are connected together, and a P type substrate and a source electrode
8
which are connected together.
A connecting point
10
between the gate electrode
3
of the depletion type MOS transistor
1
and the gate electrode
6
of the enhancement type MOS transistor
2
is connected to a connecting point
9
between the source electrode
4
of the depletion type MOS transistor
1
and the drain electrode
7
of the enhancement type MOS transistor
2
. The drain electrode
11
of the depletion type MOS transistor
1
is connected to a high voltage supply terminal, and the source electrode
8
of the enhancement transistor
2
is connected to a low voltage supply terminal. In the above circuit, a constant reference voltage is provided at output terminal
5
connected to the connecting point
9
.
FIG. 6
shows the relationship between electric current and voltage in the circuit of FIG.
5
. In
FIG. 6
, line A shows drain current as a function of gate voltage of the depletion type MOS transistor
1
, and line B shows drain current as a function of gate voltage of the enhancement type MOS transistor
2
. In these MOS transistors, the current I between the source electrode and the drain electrode (drain current) is represented by the following equation (1) in the case of a saturated condition:
I=K
(
V
g
−V
t
)
2
(1)
wherein K, V
g
and V
t
represent a conductivity coefficient, the voltage between the source and gate (gate voltage) and the threshold voltage, respectively.
Under conditions in which the drain current I
1
of the depletion type MOS transistor
1
and the drain current I
2
of the enhancement type MOS transistor
2
are used in common and the voltage V
g1
between the source electrode and the gate electrode of the depletion type MOS transistor
1
is zero, the gate voltage V
g2
between the source electrode and the gate electrode, that is, the voltage output V
C
from the constant-voltage output terminal
5
of the enhancement type MOS transistor
2
is shown by the following equation (2):
V
C
=
-
k1
k2
·
V
t1
+
V
t2
(
2
)
wherein k1 and k2 are the conductivity coefficients of the depletion type MOS transistor
1
and the enhancement type MOS transistor
2
, respectively, and V
t1
and V
t2
are the threshold voltages of these transistors, respectively.
In the conventional art, the conductivity coefficients of both transistors are set substantially equal (k1=k2) so that the relationship (V
C
=V
t2
−V
t1
) is obtained.
In
FIG. 6
, c-O is the drain current I
1
of the depletion type MOS transistor
1
, g-f is the drain current I
2
of the enhancement type MOS transistor
2
, and the constant-voltage V
C
of the source-gate voltage of the enhancement type MOS transistor
2
is represented by the length O-f. In
FIG. 6
, line A and line B have the same conductivity coefficients so that the slopes of these lines are the same.
In this device, the temperature characteristic of the threshold voltage is shown as a deviation in the amount (V
g
−V
t
) in the above equation (1). In equation (1), V
g1
=0 and k1=k2 are preconditions for the above described circuit so that the quantity (V
g
−V
t
) in equation (1) is equally utilized for the depletion type MOS transistor
1
and the enhancement type MOS transistor
2
. Accordingly, the output voltage of the semiconductor device is hardly changed with a change in ambient temperature.
In the above conventional art, even if the ambient temperature is changed, a constant output voltage is obtained at all times. However, it is sometimes desirable to utilize an electronic device in which there is a change in reference voltage corresponding to a change in ambient temperature. The above described technique cannot be applied in that case. In the conventional art, temperature compensation of a reference voltage corresponding to the ambient temperature is difficult to accomplish.
It is also difficult to provide an oscillator having a reference voltage output semiconductor device used for controlling the oscillation frequency of the crystal oscillator, wherein the reference voltage output changes in a predetermined manner depending on the ambient temperature.
SUMMARY OF THE INVENTION
In view of the above problems of the prior art, it is therefore an object of the present invention to provide semiconductor device having a reference voltage output which varies in accordance with the ambient temperature.
In a first embodiment, the present invention provides a semiconductor device for outputting a reference voltage having a depletion type MOS transistor and an enhancement type MOS transistor which are connected in series. The conductivity coefficient of at least one of these transistors is variable, and the conductivity coefficients of both of the transistors are different from one another.
The value of the reference voltage output from the semiconductor device depends on the threshold voltage of the depletion type MOS transistor, the threshold voltage of the enhancement type MOS transistor, and the conductivity coefficients of both types of transistors. The temperature characteristic of the output reference voltage is obtained by differentiating the voltage value calculated from the above values with respect to temperature. The value thus obtained varies as a function of the ambient temperature. The temperature characteristic of the threshold voltage has a slope which decreases with an increase in ambient temperature. If the conductivity coefficient of the depletion type MOS transistor is less than the conductivity coefficient of the enhancement type MOS transistor, the temperature characteristic of the output reference voltage has a slope which decreases with an increase in ambient temperature.
A semiconductor device for outputting a reference voltage in accordance with a second embodiment of the present invention has the same transistors as described above. However, the conductivity coefficients of both of the transistors are variable.
A semiconductor device for outputting a reference voltage in accordance with a third embodiment of the present invention has at least one depletion type MOS transistor and at least one enhancement type MOS transistor having changeable sizes so as to adjust the respective conductivity coefficients. The term “size” as used herein means the ratio of L/W. L is adjusted by selecting a number of transistors connected in series. W is adjusted by selecting a number of transistors connected in parallel. In the present invention, L and W are changeable, for example, by cutting fuses between transisto
A & Cmos Communications Device Inc.
Kim Jung Ho
Sughrue Mion Zinn Macpeak & Seas, PLLC
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