Semiconductor device for generating constant potential

Details Semiconductor device for generating constant potential Semiconductor device for generating constant potential

1992-04-29

1994-06-07

Wambach, Margaret R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072962, 3072964, 3072965, 307473, 307270, H03K 301, H03K 326

Patent

active

053192567

ABSTRACT:
A constant potential generating semiconductor device includes: an output circuit having a first channel type first transistor and a second channel type second transistor serially connected between a first power source and a second power source V.sub.ss, a connection point between the first and second transistors being connected to an output terminal; a reference potential generating circuit having a first current limiter, a first channel type third transistor, a second channel type fourth transistor, and a second current limiter serially connected between a first power source and a fourth power source, a first connection point interconnecting the first current limiter and the third transistor being connected to the gate of the first transistor, a second connection point interconnecting the fourth transistor and the second current limiter being connected to the gate of the second transistor, the first connection point being connected to the gate of the third transistor, and the gate of the fourth transistor being connected to the second connection point; an output mode switching circuit having a fifth transistor and a sixth transistor, the fifth transistor interconnecting the gate of the first transistor and a fifth power source at a fourth connection point, the sixth transistor interconnecting the gate of the second transistor and a sixth power source at a fifth connection point, the output mode switching circuit having a switching input terminal, a switching signal for switching an output mode being applied to the switching mode input terminal, the switching input terminal being connected to the gates of the fifth and sixth transistors, during a first output mode with a first level signal being applied to the switching input terminal, both the fifth and sixth transistors turning off to maintain the connection between the gates of the first and second transistors and the first and second connection points, respectively, and during a second output mode with a second level signal being applied to the switching input terminal, both the fifth and sixth transistors turning on to electrically disconnect the gates of the first and second transistors from the first and second connection points, respectively; and a potential difference suppressing circuit for suppressing a potential difference between the gate and back gate of the fourth transistor during the second output mode.

REFERENCES:
patent: 4691123 (1987-09-01), Hashimoto et al.

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