Semiconductor device for clock signals synchronization accuracy

Details Semiconductor device for clock signals synchronization accuracy Semiconductor device for clock signals synchronization accuracy

2002-03-27

2004-11-16

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000

Reexamination Certificate

active

06819153

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor devices and, more particularly, to a semiconductor device which generates a clock signal that is synchronized with a reference signal, like a horizontal synchronizing signal in a video signal.
BACKGROUND OF THE INVENTION
In recent years, video signal processing in digital has been advancing, and semiconductor devices for synchronizing a clock that is employed in the video signal processing with reference signal like a horizontal synchronizing signal in a video signal are utilized in the video signal processing.
Hereinafter, these conventional semiconductor devices will be described.
A first prior art is described with reference to
FIGS. 9
,
11
,
12
and
13
.
FIG. 9
is a circuit diagram illustrating a prior art semiconductor device.
In
FIG. 9
, a reference signal input terminal
101
receives a reference signal. A phase comparator
102
compares an output of a dividing circuit
105
with the reference signal to generate a difference signal, and outputs the difference signal as a phase difference output. A low-pass filter (hereinafter, referred to as LPF)
103
converts the phase difference signal that is outputted from the phase comparator
102
into a voltage, and outputs an obtained voltage as a control voltage for controlling a VCO
104
. The VCO
104
is controlled by the control voltage that is outputted from the LPF
103
, and converts a clock frequency on the basis of the phase difference to output a synchronous clock (sync clock). The dividing circuit
105
divides the sync clock that is outputted from the VCO
104
, and outputs the obtained signal to the phase comparator
102
as a comparison signal. The sync clock that is outputted from the VCO
104
is outputted to the outside from a clock output terminal
106
.
FIG. 11
is a circuit diagram illustrating the phase comparator
102
shown in FIG.
9
. Reference numeral
110
denotes a target signal input terminal. Numeral
111
denotes a comparison signal input terminal. Numeral
112
denotes a phase difference output terminal. FIGS.
12
(
a
) to
12
(
c
) are timing charts for explaining the phase comparator
102
shown in FIG.
11
. FIG.
12
(
a
) shows a signal waveform of a target signal that is inputted to the target signal input terminal
110
. FIG.
12
(
b
) shows a signal waveform of a comparison signal that is inputted to the comparison signal input terminal
111
. FIG.
12
(
c
) shows a signal waveform of a phase difference output that is outputted from the phase difference output terminal
112
.
FIG. 13
is a circuit diagram illustrating the LPF
103
shown in FIG.
9
. Numeral
120
denotes a phase difference input terminal. Numerals
121
and
122
denote resistors. Numerals
123
and
124
denote capacitors. Numeral
125
denotes a control voltage output terminal. The LPF
103
constituted as described above converts the phase difference signal which is outputted from the phase comparator
102
and is inputted to the phase difference input terminal
120
into a voltage, and outputs the obtained voltage from the control voltage output terminal
125
as a control voltage for controlling the VCO
104
.
Next, the operation of the first prior art semiconductor device will be described.
The reference signal that is inputted through the reference signal input terminal
101
is inputted to the phase comparator
102
as a target signal. A clock that is synchronized with the reference signal is generated by the VCO
104
and is outputted to the dividing circuit
105
as well as to the outside through the clock output terminal
106
.
The sync clock inputted to the dividing circuit
105
is frequency-divided by the dividing circuit
105
, and the divided clock is inputted to the phase comparator
102
as a comparison signal. At this time, the dividing circuit
105
divides the sync clock so that the frequency of the reference signal coincides with the frequency of the comparison signal.
The phase comparator
102
compares the comparison signal with the reference signal as the target signal to generate a difference signal, and outputs the difference signal as a phase difference output.
As the phase comparator
102
, a phase comparator shown in
FIG. 11
is commonly used. The reference signal is inputted as a target signal to the target signal input terminal
110
, and the signal obtained by the dividing circuit
105
is inputted to the comparison signal input terminal
111
as a comparison signal. When a change point of the target signal is located before a change point of the comparison signal as shown in
FIG. 12
, an H pulse corresponding to the phase difference is outputted to the phase difference output terminal
112
as a phase difference output. When the change point of the target signal is located behind the change point of the comparison signal, an L pulse corresponding to the phase difference is outputted to the phase difference output terminal
112
as a phase difference output.
Then, the phase difference output that is a pulse outputted from the phase comparator
102
is inputted to the LPF
103
, and is converted into a voltage for controlling the VCO
104
to be inputted to the VCO
104
as a control voltage.
Then, the VCO
104
is controlled by the control voltage outputted from the LPF
103
, and changes the frequency of the clock outputted from the VCO
104
by the phase difference.
By repeating the above-mentioned operation until the phase comparator
102
comes to detect no phase difference between the signal obtained by the dividing circuit
105
and the reference signal inputted through the reference signal input terminal
101
, a clock signal that is synchronized with the reference signal which is inputted through the reference signal input terminal
101
can be generated, and a clock signal synchronized with the reference signal can be outputted from the clock output terminal
106
.
A second prior art will be described with reference to FIG.
10
.
FIG. 10
is a circuit diagram illustrating a prior art semiconductor device for synchronizing a clock with a reference signal. Numeral
131
denotes a clock input terminal. Numerals
132
to
139
denote buffers. Numeral
140
denotes a reference signal input terminal. Numeral
141
denotes a selector. Numeral
142
denotes a sync clock output terminal.
Next, the operation of the prior art semiconductor device for synchronizing a clock with a reference signal is described.
A clock having the same frequency as that of a desired clock is inputted to the clock input terminal
131
. The inputted clock is delayed by the buffers
132
to
139
, and clocks which are slightly shifted in phase with each other are outputted from the respective buffers.
The selector
141
selects a clock having a phase closest to that of the reference signal that is inputted through the reference signal input terminal
140
, from the clocks having the various phases which are outputted from the respective buffers
132
to
139
, and outputs the selected clock as a sync clock from the sync clock output terminal
142
.
As described above, in this second prior art, the selector
141
selects a clock having a phase closest to that of the reference signal, thereby obtaining a clock synchronized with the reference signal.
However, in the first prior art, the sync clock is generated by repeating the phase comparison between the reference signal inputted through the reference signal input terminal
101
and a clock signal to be synchronized with the reference signal by means of the phase comparator
102
. Therefore, when the phase of the reference signal varies abruptly, it is hard for the sync clock to follow the reference signal. Further, in order to keep the frequency of the sync clock constant, it is required to keep the control voltage of the VCO
104
at a constant value after clock synchronization with the reference signal is performed and before the next reference signal is inputted. However, when the interval between the reference signals is large, the oscillated frequency of the VCO
104
varies due to

Affiliated with

Also associated with

Rating

Semiconductor device for clock signals synchronization accuracy does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device for clock signals synchronization accuracy, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device for clock signals synchronization accuracy will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3352055