Semiconductor device featuring overlay-mark used in...

Details Semiconductor device featuring overlay-mark used in... Semiconductor device featuring overlay-mark used in...

2008-07-22

2008-07-22

Dang, Trung (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C257SE23179

Reexamination Certificate

active

07402914

ABSTRACT:
In a semiconductor device, an insulating layer formed on a substrate and a wiring pattern layer is formed on the insulating layer. A lower mark element is defined as a groove formed in the insulating layer, and defines an overlay mark in conjunction with an upper mask element formed in a photoresist pattern coated on the insulating layer for the formation of the wiring pattern layer. The lower mark element features a width falling within a range from approximately 4 to 6 μm, and a depth of at most 1 μm.

REFERENCES:
patent: 6083807 (2000-07-01), Hsu
patent: 6165656 (2000-12-01), Tomimatu
patent: 6316328 (2001-11-01), Komuro
patent: 2005/0074945 (2005-04-01), Chang
patent: 2005/0110012 (2005-05-01), Lee et al.
patent: 2006/0151890 (2006-07-01), Smith et al.
patent: 2003-31484 (2003-01-01), None

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