Semiconductor device fabrication with planar gate interconnect s

Details Semiconductor device fabrication with planar gate interconnect s Semiconductor device fabrication with planar gate interconnect s

1995-11-20

1996-10-08

Dang, Trung

Fishing, trapping, and vermin destroying

437193, 437 44, 437 40, 437 41, 437228, H01L 2144

Patent

active

055630960

ABSTRACT:
In accordance with principles of the invention, there is provided a new process for semiconductor device fabrication. The disclosed process includes forming field isolation regions on a surface of a silicon wafer, and forming gate oxide regions selectively between the field isolation regions. A gate interconnect material is deposited over the field isolation regions and gate oxide regions. A planar surface is formed on the top of the gate interconnect material. This planarization step may be accomplished by chemical mechanical polishing or some other convenient method such as a resist etch back. After planarization of the gate interconnect material, a uniform thickness photoresist is deposited on the planar surface. A gate interconnect etch pattern is formed on the planar surface using photolithography and the gate interconnect material is etched to match a gate interconnect pattern and the photoresist is removed. Sidewall spacers are provided. A silicide is formed over the top of the gate interconnect and over the diffusion areas.

REFERENCES:
patent: 4786609 (1988-11-01), Chen
patent: 5324689 (1994-06-01), Yoo
patent: 5385857 (1995-01-01), Solo de Zaldivar
patent: 5422289 (1995-06-01), Pierce

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