Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-11-21
2004-09-28
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S725000
Reexamination Certificate
active
06797637
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for accurately etching a SiN film and a BARC film.
2. Description of the Related Art
Conventionally, a method of dry-etching with a gas including CF
4
, CHF
3
, O
2
and Ar has been proposed as a method for etching a BARC (bottom anti-reflective coating) film formed on an underlying SiN film.
FIGS. 12
to
14
are diagrams showing variations in cross-section of a gate structure having a step. In the case shown, the BARC film is formed at a predetermined portion in the gate structure by dry-etching with the aforementioned method.
In this gate structure, the step is formed, as shown in
FIG. 12
, by layering a polySi film
102
, a WSi film
103
, a SiN film
104
and a BARC film
105
, in this order, on a substrate
100
at which a LOCOS (local oxidization of silicon) region
101
is formed. When the BARC film is etched with the aforementioned gas, a BARC residue
105
′ at a step depression portion is generated in the etching process, as shown in FIG.
13
.
The SiN film
104
is a hard mask for protecting the underlying films (i.e., the polySi film
102
and the WSi film
103
). When over-etching is performed in order to remove the BARC residue
105
′, an etching amount is 1.8 times as that of the BARC film. Consequently, as shown in
FIG. 14
, a portion of the etched SiN film
104
′ that is protected by the BARC residue
105
′ at the step depression portion is thicker than other parts of the SiN film
104
′. Thus, the thickness of the SiN film
104
′ becomes non-uniform. In this case, portions of the SiN film
104
′ that are not protected by the BARC residue
105
′ become excessively thin due to the etching.
In the circumstances described above, when further etching is performed on the SiN film
104
′, because there are large variations in the thickness of the SiN film
104
′, it is difficult to reliably perform subsequent etching of the underlying films with high accuracy, even if a selectivity ratio relative to the underlying films is adequate.
FIG. 15
is a diagram which schematically shows the form of a pattern in the case of formation by a usual hard mask etching process of the prior art, that is, a process of using etching gas of CHF
3
/O
2
/Ar with flow rates of 20/5/400 (SCCM) in a magnetron RIE (reactive ion etching) device, and then performing etching of an SiN/SiO
2
film
111
, which is a hard mask for protecting a polySi film
110
, under etching conditions of: substrate RF power=500 W; pressure=40 mTorr; and electrode temperature=40° C.
As is shown in
FIG. 15
, the SiN film is etched substantially vertically at high-density pattern portions having a high degree of integration, such as, for example, cell portions for a DRAM. However, low-density pattern portions, peripheral portions and the like, which gas that tends to cause deposition can easily enter, become tapered due to the effect of deposition material. Thus, there is a problem in that lateral dimensions vary in relation to density variations of the pattern.
SUMMARY OF THE INVENTION
A main object of the present invention is to provide a semiconductor device fabrication method which, at a time of etching a BARC film, can increase an etching selectivity ratio of underlying films and enables optimal etching regardless of a degree of density variation of a pattern, and which, at a time of hard mask etching of a SiN film or the like, enables optimal etching regardless of the degree of density variation of the pattern.
According to a first aspect of the present invention, in a semiconductor device fabrication method which includes etching a BARC film disposed with an underlying SiN or polySi film, the etching of the BARC film includes dry-etching the BARC film with etching gas in which at least O
2
, Cl
2
and He are mixed with predetermined flow volume ratios; and when an etching selectivity ratio of the BARC film relative to the underlying film is to be made larger, increasing the flow volume ratio of O
2
relative to Cl
2
.
According to a second aspect of the present invention, in a semiconductor device fabrication method which includes etching a BARC film disposed with an underlying SiN or polySi film, the etching of the BARC film includes dry-etching the BARC film with etching gas in which at least O
2
, Cl
2
and He are mixed with predetermined flow volume ratios; and when an etching selectivity ratio of the BARC film relative to the underlying film is to be made larger, reducing ion energy at the time of etching.
According to a third aspect of the present invention, in a semiconductor device fabrication method which includes etching a BARC film disposed with an underlying SiN or polySi film, the step of etching the BARC film includes dry-etching the BARC film with etching gas in which at least O
2
, Cl
2
and He are mixed with predetermined flow volume ratios; and setting the flow volume ratio of O
2
relative to Cl
2
in the etching gas to at least 1.
According to a fourth aspect of the present invention, in a semiconductor device fabrication method which includes etching a SiN film, the etching of the SiN film includes: at the time of etching the SiN film, using etching gas in which HBr, CF
4
and He are mixed in predetermined flow volume ratios; and setting ion energy at the time of etching in a range from 13 eV to 30 eV.
REFERENCES:
patent: 5188704 (1993-02-01), Babie et al.
patent: 5431772 (1995-07-01), Babie et al.
patent: 6417083 (2002-07-01), Mori
patent: 6451647 (2002-09-01), Yang et al.
patent: 2001/0036732 (2001-11-01), Yoshida et al.
patent: 2003/0029835 (2003-02-01), Yauw et al.
patent: 163-691 (2000-12-01), None
patent: 3-145725 (1991-06-01), None
patent: 10303180 (1998-11-01), None
patent: 2000-133633 (2000-05-01), None
patent: 2001-208497 (2000-07-01), None
patent: 2001-3185 (2001-01-01), None
patent: 2001-308076 (2001-11-01), None
Le Dung A.
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
LandOfFree
Semiconductor device fabrication method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device fabrication method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device fabrication method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3244937