Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2005-01-25
2005-01-25
Mengistu, Amare (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S100000, C712S011000
Reexamination Certificate
active
06847346
ABSTRACT:
A transfer circuit25includes two sets of an input circuit52A and an output circuit53B, which allows bidirectional transfer. The input circuit52A decomposes external input data signals DI11A and DI12A to signals on lines L11to L14in synchronism with a clock signal CLK in order to reduce the frequency thereof. The output circuit53B composes the decomposed signals in synchronism with the clock signal CLK to regenerate the original signals and output them as external output data signals DO11B and DO12B. Signals on either the lines L11to L14or L21to L24are selected by a multiplexer57to provide to a main body circuit.
REFERENCES:
patent: 5671432 (1997-09-01), Bertolet et al.
patent: 5848289 (1998-12-01), Studor et al.
patent: 6385635 (2002-05-01), Ishii
patent: 20020114415 (2002-08-01), Lee et al.
patent: 20030231734 (2003-12-01), Fujita et al.
patent: 2001-202052 (2001-07-01), None
Kumagai Masao
Udo Shinya
Arent & Fox PLLC
Fujitsu Limited
Mengistu Amare
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