Semiconductor device equipped with a pull-down circuit

Details Semiconductor device equipped with a pull-down circuit Semiconductor device equipped with a pull-down circuit

2011-03-08

2011-03-08

Nguyen, Hai L (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S427000

Reexamination Certificate

active

07902895

ABSTRACT:
Provided is a semiconductor device equipped with a pull-down circuit capable of reducing its area. The pull-down circuit is formed of a depletion type NMOS transistor in which a gate thereof is connected to a ground potential, and an enhancement type NMOS transistor in which a gate and a drain thereof are connected to a source of the depletion type NMOS transistor and a source thereof is connected to the ground potential. An overdrive voltage of the depletion type NMOS transistor is reduced by a threshold voltage of the enhancement type NMOS transistor, whereby a size of the depletion type NMOS transistor can be reduced. Accordingly, an area of the pull-down circuit can be reduced.

REFERENCES:
patent: 6091264 (2000-07-01), Kirsch et al.
patent: 6714053 (2004-03-01), Mohan
patent: 6882203 (2005-04-01), Miyagi
patent: 2003/0214337 (2003-11-01), Miyagi
patent: 2003-332892 (2003-11-01), None

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