Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
2001-02-06
2004-05-11
Ngo, Julie-Huyen L. (Department: 2871)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
C349S040000, C349S046000, C349S187000, C430S030000, C348S128000
Reexamination Certificate
active
06734940
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a semiconductor device, an electro-optical device substrate, a liquid crystal device substrate and a manufacturing method therefor, a liquid crystal device, and an electronic apparatus using the liquid crystal device. Particularly, the present invention relates to a technique for protecting circuits and elements on a substrate from static electricity produced in the process for manufacturing a liquid crystal device substrate and electric charge accumulated on the surface of an insulating substrate.
2. Description of the Related Art
In a liquid crystal cell which constitutes a liquid crystal device, for example, a plurality of data lines and a plurality of scanning lines are formed in a lattice form, and an active substrate and a counter substrate are disposed with a predetermined space therebetween. On the active matrix substrate, pixel electrodes, thin film transistors (abbreviated to “TFT” hereinafter) serving as pixel electrode drive switching elements, and the like are arranged in a matrix. On the counter substrate, a counter electrode, and the like are arranged. The active matrix substrate and the counter substrate are combined together by a sealing material containing a spacer so that the electrode formation surfaces thereof are opposed to each other with a predetermined space therebetween. A liquid crystal is sealed between both substrates.
SUMMARY OF THE INVENTION
In manufacturing the active matrix substrate having the above construction, TFTs are formed by using a semiconductor manufacturing process. However, in some cases, the substrate is charged with static electricity during the many steps of the manufacturing process, and electric charge is accumulated on the surface of the substrate due to the influence of the plasma processing step, or the like. Particularly, in the active matrix substrate for a liquid crystal device using an insulating substrate made of glass, quartz, or the like, there is no escape for the charged static electricity and accumulated charge, and thus defects such as electrostatic damage to TFTs, characteristic failures, etc. occur due to the presence of the static electricity and electric charge in some cases.
Therefore, a measure is taken in which wiring as a measure for static electricity is provided along the periphery of the substrate, and short-circuit wiring is formed to electrically connect signal lines such as scanning lines and data lines in the course of the manufacturing process so that the static electricity produced in the manufacturing process and electric charge are diffused to the wiring as the measure for static electricity in the periphery of the substrate through the short-circuit wiring, preventing unexpected excessive current due to the static electricity and electric charge from flowing into the internal TFTs, etc. Although the short-circuit wiring is required for protecting the elements such as the TFTs and wiring from static electricity in the course of the manufacturing process, the short-circuit wiring is not required after the manufacturing process. In addition, since inspection cannot be performed in a state wherein the signal lines are short-circuited in the step of inspecting electric properties, and the like, the short-circuit wiring must be cut by any method after the completion of the manufacturing process.
Therefore, the applicant proposed the method of forming and cutting short-circuit wiring disclosed in Japanese Unexamined Patent Publication No. 11-95257. This method is a method in which short-circuit wiring is formed and cut at the same time as the step of depositing any of various films, patterning, forming contact holes, etching, or the like, and is thus an excellent method because a special step for forming and cutting the short-circuit wiring need not be added. The construction of short-circuit wiring and the method of forming and cutting it disclosed in the above publication will be described below with reference to the drawings.
FIG. 2
is a schematic drawing of the construction of an active matrix substrate. As shown in this figure, in the active matrix substrate
7
, a plurality of scanning lines
4
and a plurality of data lines
3
are provided on an insulating substrate
12
so as to cross each other, and pixels
8
are formed in a matrix in the respective regions partitioned by the scanning lines
4
and the data lines
3
. The scanning lines
4
may be made of a polycrystalline silicon film, and the data lines
3
may be made of a metal film of aluminum or the like. The region where a plurality of pixels
8
are formed in a matrix is a pixel region
9
(image display region). In the periphery of the pixel region
9
, a data line driving circuit
10
is formed for supplying image signals to the plurality of data lines
3
, and scanning line driving circuits
11
are formed at both ends of the scanning lines
4
, for supplying scanning signals for image selection to the scanning lines
4
.
In the active matrix substrate
7
, as a measure for static electricity, first short-circuit wiring
41
is formed for electrically connecting all signal wiring
16
and
17
. Also, second short-circuit wiring
42
is formed for electrically connecting all scanning lines
4
. Furthermore, third short-circuit wiring
43
is formed for electrically connecting all data lines
3
. All short-circuit wiring
41
,
42
and
43
, which may be made of a polycrystalline silicon film of the same layer as the scanning lines
4
, are electrically connected to each other. In
FIG. 2
, positions marked with “x” in the course of each of the short-circuit wiring
41
,
42
and
43
is a cutting portion where each of the short-circuit wiring
41
,
42
and
43
is cut after use.
FIG. 34
is an enlarged plan view showing the corner of a pixel region
9
of an active matrix substrate
7
. As shown in this figure, pixel switching TFTs
2
are respectively provided in the pixels
8
to be connected to the scanning lines
4
and the data lines
3
, and capacitance lines
6
are extended over a plurality of the pixels
8
. As shown in FIGS.
43
(A)-(C) which will be referred to below, each of the TFTs
2
may include a gate electrode
20
formed integrally with the scanning lines
4
, and a semiconductor active film
27
which may include source regions
25
a
and
25
b
electrically connected to the data line
3
through a source contact hole
23
, which passes through a first interlayer insulating film
21
, and drain regions
26
a
and
26
b
electrically connected to a pixel electrode
1
through a drain contact hole
24
which passes through the first interlayer insulating film
21
and a second interlayer insulating film
22
. The second short-circuit wiring
42
for electrically connecting the scanning lines
4
, and the third short-circuit wiring
43
for electrically connecting the data lines
3
are formed as shown in FIG.
34
. In this drawing, reference numeral
37
denotes a cutting portion of each of the short-circuit wiring
42
and
43
, specifically a hole pattern (referred to as a “cutting hole” hereinafter) passing through the first interlayer insulating film
21
and the second interlayer insulating film
22
.
FIG. 35
is a plan view showing the connecting structure between signal wiring and short-circuit wiring in the active matrix substrate
7
shown in FIG.
34
. As shown in this figure, signal wiring
16
and
17
which may be made of a metal film of aluminum or the like, and are located in a layer different from the first short-circuit wiring
41
. Therefore, the signal wiring
16
and
17
are electrically connected to the first short-circuit wiring
41
through contact holes
34
passing through the first interlayer insulating film
21
located therebetween. This connecting structure applies to the data lines
3
, i.e., the data lines
3
are electrically connected to the third short-circuit wiring
43
through the contact holes
34
passing through the first interlayer insulating film
21
located therebetween. Like the seco
Ngo Julie-Huyen L.
Oliff & Berridg,e PLC
Seiko Epson Corporation
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