Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
1998-06-11
2002-10-15
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S758000
Reexamination Certificate
active
06465806
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device including a connection structure having two conductive patterns connected to each other through an insulative layer, a method for producing the same, and a display device including such a connection structure.
2. Description of the Related Art
As is well-known, there are various types of semiconductor devices. One type of semiconductor device is an active matrix liquid crystal display device.
FIG. 13
is a block diagram illustrating an exemplary structure of a conventional active matrix liquid crystal display device.
The active matrix liquid crystal display device shown in
FIG. 13
includes two substrates located opposed to each other and a liquid crystal layer interposed therebetween (not shown). One of the substrates (represented by chain line
110
) includes a plurality of scanning lines
101
and a plurality of signal lines
102
which are arranged perpendicular to each other. A pixel electrode
103
is provided at each of intersections of the scanning lines
101
and the signal lines
102
. Although not shown, the other substrate includes a counter electrode facing the pixel electrodes
103
. The pixel electrodes
103
arranged along each scanning line
101
are commonly connected to the scanning line
101
via corresponding switching elements, and the pixel electrodes
103
arranged along each signal line
102
are commonly connected to the signal line
102
via corresponding switching elements.
The liquid crystal display device shown in
FIG. 13
further includes a scanning line driving circuit
104
, a control circuit
105
, a voltage generation circuit
106
, and a signal line driving circuit
107
.
In one horizontal scanning period, the scanning line driving circuit
104
selects one of the scanning lines
101
in response to signals from the control circuit
105
. Then, the scanning line driving circuit
104
applies one of voltages VGH and VGL from the voltage generation circuit
106
to the selected scanning line
101
, and applies the other voltage VGH or VGL to the other scanning lines
101
which are not selected. In response to signals from the control circuit
105
, the signal line driving circuit
107
applies the voltage VSL or VSH from the voltage generation circuit
106
to each of the signal lines
102
. The voltage generation circuit
106
applies a common voltage COM to the counter electrode (not shown). In the next scanning period,. the scanning driving circuit
104
selects another one of the scanning lines
101
. In this manner, the scanning lines
101
are sequentially selected and then the rest of the operation described above is performed.
Thus, the pixel electrodes
103
connected to each scanning line
101
are driven in each horizontal scanning period, and display corresponding to such pixel electrodes
103
is performed. In one frame, display corresponding to one image plane is performed.
In such an active matrix liquid crystal display device, the substrates are formed of quartz or glass. A switching element (not shown; e.g., thin film transistor) is provided in correspondence with each pixel electrode
103
for turning ON and OFF the pixel electrode
103
. Recently, the scanning line driving circuit
104
and the signal line driving circuit
107
are integrated on the substrate in order to reduce the cost and the size of the liquid crystal display device.
A liquid crystal display device having the driving circuits integrated on the substrate is disclosed in, for example, SID '96 DIGEST, pp. 17-20. In the liquid crystal display device disclosed in the abovementioned publication, lines which include areas to be gate electrodes of the thin film transistors are anodized. Thus, generation of hillocks and the like is prevented even when the gate electrodes are formed of aluminum-type metal materials having a relatively low resistance; and the offset length of the thin film transistors is controlled at a satisfactorily high precision. Accordingly, the operation of the thin film transistors is stabilized.
In response to a demand for a highly integrated structure, some active matrix liquid crystal display devices adopt a connection structure, in which a plurality of conductive layers are laminated with insulative layers interposed therebetween and the conductive layers are connected to one another through an opening (contact hole) in each of the insulative layers.
FIG. 14A
is a plan view of a conventional connection structure included in a semiconductor device, and
FIG. 14B
is a cross-sectional view of the connection structure taken along line C-C′ in FIG.
14
A. The connection structure shown in
FIGS. 14A and 14B
includes a first conductive layer
111
, an interlayer insulative layer
112
and a second conductive layer
113
which are sequentially laminated. The second conductive layer
113
is connected to the first conductive layer
111
through an opening
112
a
formed in the interlayer insulative layer
112
. The opening
112
a
has a smaller planar size than that of each of the first and second conductive layers
111
and
113
, and the opening
112
a
is substantially completely covered by the second conductive layer
113
.
As shown in
FIG. 14A
, the conventional connection structure has a connection section
114
in which the first conductive layer
111
and the second conductive layer
113
are connected to each other. The connection section
114
is set to have a larger planar size than that of the opening
112
a
in consideration of the precision with which the first and second conductive layers
111
and
113
can be positioned with respect to the opening
112
a
and also in consideration of the displacement of the layers
111
,
112
and
113
caused during etching, which is performed for patterning the layers
111
,
112
and
113
.
According to the design rule adopted in a usual semiconductor fabrication process, where the alignment margin or design margin is &lgr;, the minimum width of the pattern of a conductive layer is 2&lgr; and the distance between two adjacent patterns of the conductive layer is 2&lgr;. In the case of the display device shown in
FIGS. 14A and 14B
, the minimum value for width W
1
of a pattern of the second conductive layer
113
(hereinafter, referred to the “second conductive layer pattern
113
” for simplicity) is 2&lgr;, and alignment margin M
1
required. for each of two ends of the second conductive layer pattern
113
in the width direction is &lgr;. The connection section
114
needs to be extended in the width direction beyond edges
113
a
and
113
b
of the second conductive layer pattern
113
so as to accommodate the two alignment margins (2&lgr;). The distance between two adjacent second conductive layer patterns
113
(only one is shown in
FIGS. 14A and 14B
) in the width direction is 2&lgr;. As a result, a width of 8&lgr; is required to provide one second conductive layer pattern
113
. In the case where a plurality of second conductive layer patterns
113
are arranged as shown in
FIG. 15
, the pitch of the second conductive layer patterns
113
is at least 5&lgr; (sum of the width 2&lgr; of each second conductive layer pattern
113
, the alignment margin &lgr; and the distance 2&lgr; between one connection section
114
and an adjacent second conductive layer pattern
113
).
In the case where the driving circuits are integrated on one substrate as described above, output stages of a driving circuit are provided in correspondence with the scanning lines and/or the signal lines. The output stages need to be arranged at the same pitch as that of the pixel electrodes, which requires an increased density of lines and other elements. Especially in the fields of high precision liquid crystal panels and liquid crystal panels to be used in conjunction with projectors, the pitch of the pixel electrodes is sometimes as small as 30 &mgr;m or less. Accordingly, the connection section
114
is demanded to have a minimum possible width.
In order to anodize the gate electrodes o
Hongyong Zhang
Kubota Yasushi
Sakai Tamotsu
Shiraki Ichiro
Nixon & Vanderhye P.C.
Prenty Mark V.
Sharp Kabushiki Kaisha
LandOfFree
Semiconductor device, display device, and method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device, display device, and method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device, display device, and method for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2998440