Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead
Reexamination Certificate
1999-11-05
2001-05-22
Picardat, Kevin M. (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
C257S737000, C257S738000
Reexamination Certificate
active
06236112
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device fabricated in a size which is approximately the same as that of a semiconductor element, and also relates to a connecting substrate used in such a semiconductor device and a method of manufacturing the connecting device.
2. Description of the Related Art
A chip sized package (CSP) is a semiconductor device fabricated in a size which is approximately the same as that of a semiconductor element, and is provided on its mounting face with external connection terminals such as solder bumps so as to be capable of being mounted on a mounting substrate by use of the external connection terminals. In general, external connection terminals are arranged, in an array, on a mounting face of a chip sized package to cope with multi-pin arrangement required of advanced semiconductor devices.
FIG. 7
illustrates an example in which terminals
14
to be subsequently connected with external connection terminals are arranged on a mounting face of a semiconductor element
10
. In the drawing, electrodes formed on the mounting face of the semiconductor element
10
are designated by reference numeral
12
, and patterned wirings for the connection between the electrodes
12
and the terminals
14
are designated by
16
.
The terminals
14
are arranged in an array on the face, on which electrode terminals are formed, of the semiconductor element
10
by, for example, a method in which, as shown in
FIG. 8
, the patterned wirings
16
are rerouted on the surface of a passivation film
8
of the semiconductor element
10
, and the terminal
14
is provided at an end of the patterned wiring
16
, or a method in which a wiring patterned film having terminals provided in a given arrangement is bonded to the electrode/terminal-formed face of the semiconductor element through a buffer layer. The patterned wirings
16
are located on an insulation film formed on the passivation film
8
, although the insulation film is not shown in FIG.
8
.
The electrode terminal
14
to be connected with the external connection terminal
26
(
FIG. 8
) is required to have a diameter of an order of 300 micrometers. Accordingly, if the terminals
14
are positioned directly on electrode/terminal-formed face of the semiconductor element
10
, the distance between adjacent terminals
14
is narrower, and the space where the patterned wirings
16
are arranged is restricted. Arranging the electrodes
12
at a higher density to increase the number of electrodes
12
results in an increase in the number of patterned wirings
16
connecting the electrodes
12
to the terminals
14
, which makes it more difficult to obtain the space where the patterned wirings
16
are rerouted.
Although it is envisaged that the patterned wirings
16
are formed in multiple layers when the patterned wirings
16
cannot be rerouted within the electrode/terminal-formed face of the semiconductor element
10
, forming the patterned wirings
16
in multiple layers raises problems with respect to a complicated manufacturing process and reliability of products.
Also, when the buffer layer and wiring patterned film were used as interposers to electrically connect the electrodes
12
of the semiconductor element
10
to the terminals provided on the wiring patterned film, there were problems of complexities of a process for the manufacture of the wiring patterned film and operations for the manufacture of semiconductor devices.
SUMMARY OF THE INVENTION
The invention aims to provide a connecting substrate and a process of the manufacture thereof, the connecting substrate having a simpler structure compared with conventional interposers to thereby make it possible to easily and less expensively manufacture semiconductor devices fabricated in a size which is approximately the same as that of a semiconductor element, and also provide a semiconductor device produced using the connecting substrate.
Thus, the invention provides a semiconductor device having a semiconductor element and a connecting substrate, wherein the connecting substrate comprises a flat sheet-like insulation member having first and second surfaces, the first surface being provided with solder bumps projecting from the first surface at the locations corresponding to the locations of electrodes on an electrode/terminal-formed face of the semiconductor element or terminals formed at ends of patterned wirings formed by rerouting a conductive material on the electrode/terminal-formed face, the second surface being provided with external connection terminals which have a larger diameter than that of the solder bump on the first surface and are electrically connected with the solder bumps through a via piercing the insulation member in the direction of its thickness, and wherein the semiconductor element is mounted on the connecting substrate by bonding the electrodes or the terminals on the electrode/terminal-formed face of the semiconductor element to the solder bumps.
Preferably, an underfiller material is filled in the gap between the electrode/terminal-formed face of the semiconductor element and the insulation member.
Preferably, the insulation member is made of a material having Young's moduli of not greater than 500 MPa near room temperature and not greater than 50 MPa near 150° C.
Preferably, the via is formed by filling a hole penetrating the insulation member with solder.
Preferably, the via is formed by filling most of a hole penetrating the insulation member with copper material.
The invention also provides a connecting substrate used to produce a semiconductor device, which comprises a flat sheet-like insulation member having first and second surfaces, the first surface being provided with solder bumps projecting from the first surface at the locations corresponding to the locations of electrodes on an electrode/terminal-formed face of the semiconductor element or terminals formed at ends of patterned wirings formed by rerouting a conductive material on the electrode/terminal-formed face, the second surface being provided with external connection terminals which have a larger diameter than that of the solder bump on the first surface and are electrically connected with the solder bumps through a via piercing the insulation member in the direction of its thickness.
Preferably, the insulation member is made of a material having Young's moduli of not greater than 500 MPa near room temperature and not greater than 50 MPa near 150° C.
Preferably, the via is formed by filling a hole penetrating the insulation member with solder.
Preferably, the via is formed by filling most of a hole penetrating the insulation member with copper material.
The invention further provides a process of the manufacture of a connecting substrate used to produce a semiconductor device, which comprises:
preparing a flat sheet-like insulation member having a first surface covered with a copper foil and a second surface with no cover;
piercing holes in the insulation member, at the locations corresponding to the locations of electrodes on an electrode/terminal-formed face of a semiconductor element or terminals formed at ends of patterned wirings formed by rerouting a conductive material on the electrode/terminal-formed face, the holes piercing through the insulation member in the direction of its thickness to expose portions of the back side of the foil;
forming a resist pattern on the surface side of the copper foil, the resist pattern having holes having a larger diameter than that of the hole piercing the insulation member to expose portions of the surface side of the copper foil in a concentrical relationship with the holes piercing the insulation member;
plating the exposed portions of both surface and back sides of the foil with solder using the foil as an electrical power supply layer for the plating to thereby fill the holes piercing the insulation member and the holes in the resist pattern with the solder;
removing the resist pattern to thereby expose the copper foil and leave the plated solder pa
Horiuchi Michio
Kazama Takuya
Collins D. M.
Picardat Kevin M.
Shinko Electric Industries Co. Ltd.
Staas & Halsey , LLP
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