Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
2002-07-30
2004-10-26
Kielin, Erik J. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S351000, C257S373000, C438S514000, C438S554000
Reexamination Certificate
active
06809336
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof and, in particular, to a semiconductor device comprising a sense amplifier such as a DRAM (dynamic random access memory), as well as a method of manufacturing the same.
2. Description of the Background Art
Memory Cell Configuration
As example of DRAMs,
FIG. 17
shows the configuration of a memory cell part of a one-transistor cell DRAM
90
having one N-channel MOS transistor (NMOS transistor) per memory cell.
In
FIG. 17
, memory cells MC
0
, MC
1
, MC
2
, and MC
3
having NMOS transistors M
0
, M
1
, M
2
, and M
3
, respectively, are disposed in four portions at which two data lines DL
0
and DL
1
disposed in parallel and two word lines WL
0
and WL
1
disposed in parallel cross each other.
A gate electrode and drain electrode of the NMOS transistor M
0
are connected to the word line WL
0
and data line DL
0
. A gate electrode and drain electrode of the NMOS transistor M
1
are connected to the word line WL
0
and data line DL
1
. A gate electrode and drain electrode of the NMOS transistor M
2
are connected to the word line WL
1
and data line DL
0
. The gate electrode and drain electrode of the NMOS transistor M
3
are connected to the word line WL
1
and data line DL
1
.
A capacitor CS is connected between each source electrode and each ground potential of the NMOS transistors M
0
, M
1
, M
2
, and M
3
.
A sense amplifier SA is connected to the data lines DL
0
and DL
1
, respectively. Connections and non-connections of one terminal of the data line DL
0
and one terminal of the data line DL
1
to a data input-output line IO are controlled by column selection switches CW
0
and CW
1
. The sense amplifier SA has switches SW
0
and SW
1
, the operations of which are controlled by a sense amplifier drive signal.
Connection and non-connection of the other terminal of the data line DL
0
and the other terminal of the data line DL
1
to a precharge voltage supply line PL are controlled by precharge switches PW
0
and PW
1
. A capacity CD parasitizes the data lines DL
0
and DL
1
.
Operation of the DRAM
90
will next be described by referring to FIG.
17
.
Precharge Operation
In a DRAM, a precharge operation is performed prior to the operation of a memory cell. In the precharge operation, the data lines DL
0
and DL
1
are set to a predetermined precharge voltage VP, and the precharge voltage VP is generally a half of a write voltage VDD (VP=VDD/2).
Power consumption and noise when charging and discharging the data lines can be reduced by setting the precharge voltage VP to an intermediate value between the write voltage VDD to the capacitor and 0 V.
Turning on a precharge clock starts the precharge operation. Turning off the precharge clock results in that the precharge voltage VP is held in a floating state by a parasitic capacity CD of the data line.
Read Operation
Operation of reading the data of a specific memory cell, e.g., a memory cell M
0
, will be described below.
First, select the word line WL
0
to which the memory cell M
0
is connected, and apply a pulse voltage (word pulse). Thereby, a signal voltage VS that corresponds to an information voltage (VDD or 0 V) of the capacitor CS in the memory cell M
0
is superimposed to the precharge voltage VP, and the resulting voltage is then outputted to the data line DL
0
, as a positive or negative signal. Note that the operation of outputting the capacitor information to the data line is hereinafter referred to as “data calling,” in some cases. The signal voltage VS can be expressed in the following equation (1).
VS=VDD
/2
·CS/CS+CD
(1)
In general, the capacity of the capacitor CS is far smaller than the parasitic capacity CD. The modem trend in reducing the area of a semiconductor chip is toward smaller memory cell and connection between one data line and more memory cells. Therefore, there has been tendency toward further small capacitor CS and further large parasitic capacity CD.
The signal voltage VS that is a small positive or negative signal is detected and amplified by the sense amplifier SA connected to the data lines DL
0
and DL
1
.
The sense amplifier SA operates by using the precharge voltage VP (VDD/2) as a reference voltage. If the signal voltage VS is greater than VDD/2, the output voltage of the sense amplifier SA becomes VDD. If smaller than VDD/2, it becomes 0.
The amplified voltage corresponding to the information of the capacitor CS is outputted to the exterior by turning on the column selection switches CW
0
and CW
1
, thereby completing the read operation. At this time, information of every non-selected memory cell (hereat, the memory cell M
1
) on the selected word line (hereat, the word line WL
0
) is also called by the data line DL
1
, and the information is amplified by the sense amplifier SA.
When a word pulse is applied, information of every memory cell on the above word line is destroyed. Specifically, since the capacity of the capacitor CS is sufficiently smaller than the parasitic capacity CD, the storage node of the capacitor CS that has been VDD or 0 V is charged to the precharge voltage, irrespective of the information voltage.
More specifically, upon application of the word pulse, the storage node voltage corresponding to a binary information changes from VDD to (VDD/2)+VS, or from 0 V to (VDD/2)−VS. That is, the voltage margin of the binary information of the storage node decreases from VDD to 2VS, resulting in the same as the state that the information is destroyed.
This requires that an individual sense amplifier be placed on all the data lines and, with the sense amplifiers, the signal voltage VS be amplified to VDD or 0 V at the same time, and then rewritten to each memory cell.
Therefore, at the time of the read operation, a sequence of operations such as calling of a small signal voltage VS, amplifying, and rewriting, are performed in parallel with respect to all the memory cells on the selected word line. Only information of a data line, to which the selected memory cell is connected, is outputted to the exterior as a read information.
Write Operation
Write operation to the selected memory cell, e.g., the memory cell M
0
, is executed by applying a word pulse to the word line WL
0
and a binary information voltage (VDD or 0 V) to the data line DL
0
.
However, as discussed above, the read operation is performed prior to the write operation, because it is necessary to prevent information destroy of the non-selected cell due to the application of the word pulse.
Specifically, the above-mentioned read operation is performed with respect to all the memory cells on the word line WL
0
, and the amplified voltage corresponding to the information of the memory cell is temporally held on the respective data lines.
Thereafter, the column selection switch CW
0
is turned on so that the amplified voltage on the selected data line DL
0
is forcedly replaced with a write information voltage from the exterior (the data input-output line IO). This is then inputted to the capacitor CS of the memory cell MC
0
that has selected the write information voltage.
At this time, the amplified voltage of all the non-selected data lines (hereat, the data line DL
1
) on the selected word line (hereat, the word line WL
0
) is rewritten to the non-selected cell (hereat, the memory cell MC
1
).
Through the foregoing operations, irrespective of the read or write operation of the selected cell, a sequence of operations such as the calling of the small signal voltage VS, amplifying, and rewriting, is performed in the non-selected memory cell on the selected word line.
In order to output a sufficient signal voltage to a data line, or write the voltage VDD to the capacitor CS, the word pulse voltage is applied as a voltage not less than the sum of the voltage VDD and the threshold voltage V
th
of a cell transistor.
Refresh Operation
Refresh operation inherent in DRAMs can be realized by that the foregoing read operation is succ
Hamamoto Takeshi
Kunikiyo Tatsuya
Tanaka Yoshinori
Kielin Erik J.
Renesas Technology Corp.
Smoot Stephen W.
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