Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
2000-12-21
2003-07-22
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S374000, C257S510000
Reexamination Certificate
active
06597026
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device with a MISFET (Metal Insulator Semiconductor Field Effect Transistor) isolated by a shallow trench isolation (STI) structure and, more particularly, to a semiconductor device with a wide-channel MISFET having a reverse narrow channel effect substantially the same as that of a narrow-channel MISFET.
As the integration degree of semiconductor devices increases, the isolation portion of a MISFET as the main element constituting the integrated circuit of a semiconductor device must also be micropatterned. To isolate a MISFET, shallow trench isolation is employed in place of an isolation structure, e.g., LOCOS (LOCal Oxidation of Silicon), which is difficult to micropattern. Shallow trench isolation is employed because of two main reasons. The first reason is that when the isolation width becomes almost 0.35 &mgr;m or less, in a LOCOS structure, the isolation breakdown voltage decreases rapidly. The second reason is a decrease in element region occurring when an oxide film bites in it, which is called a bird's beak of LOCOS. A scheme that solves these problems to decrease the pitch of elements to be arranged is shallow trench isolation. This is indispensable in high integration of elements.
In a semiconductor device integrated circuit, a plurality of MISFETs with various channel widths different from each other are formed on a single substrate. For example, a narrow-channel MISFET and a wide-channel MISFET are used as elements constituting a static random access memory and a power circuit, respectively, of one semiconductor device, and are mixedly formed on one substrate.
FIGS. 7 and 8
show a conventional semiconductor device with a plurality of MISFETs isolated by shallow trench isolation and having channel widths different from each other.
As shown in
FIGS. 7 and 8
, a conventional semiconductor device
60
has, on a silicon substrate
62
, three narrow-channel MISFETs
66
each with a small channel width W
1
and a wide-channel MISFET
68
with a large channel width W
2
respectively formed in element formation regions defined by shallow trench isolation regions
64
.
The narrow-channel MISFETs
66
and wide-channel MISFET
68
respectively have gate electrodes
72
and
74
through gate insulating films
70
. Each narrow-channel MISFET
66
has a source electrode
76
and drain electrode
78
respectively at its two channel ends. The wide-channel MISFET
68
has a source electrode
80
and drain electrode
82
respectively at its two channel ends.
The conventional semiconductor device described above has the following problems.
FIG. 10
shows the gate voltage to drain current characteristics of MISFETs with 0.2-, 1-, and 10-&mgr;m channel widths which serve as conductor paths. It is apparent from
FIG. 10
that the gate voltage to drain current characteristics of the MISFETs with 1- and 10-&mgr;m channel widths form nonlinear curves with steps. In other words, hump characteristics appear in these characteristics. The subthreshold regions of MISFETs with the 1- and 10-&mgr;m channel widths and exhibiting the hump characteristics have the same characteristics as those of the MISFET with the 0.2-&mgr;m channel width where no hump characteristic is observed.
In order to explain these phenomena, the channel of a MISFET will be analyzed by dividing it into a channel side edge portion along the shallow trench isolation region and a channel planar portion between two channel side edge portions when seen in the direction of channel width. Note that the channel side edge portion is rounded with a predetermined radius of curvature during a MISFET manufacturing process.
In a wide-channel MISFET with a shallow trench isolation structure, when a voltage is applied to the gate electrode, a gate electric field generated by the applied voltage is locally concentrated at the channel side edge portion crossing the gate electrode. Even when the same gate voltage is applied, the gate electric field becomes higher at this portion than at the channel planar portion, and the threshold voltage of the channel side edge portion becomes lower than the threshold voltage of the channel planar portion. Therefore, an inversion layer is formed in the channel side edge portion before in the channel planar portion to render an ON state, so a channel drain starts to flow undesirably.
As a result, the channel side edge portion of the MISFET where the threshold voltage is low and the channel planar portion of the MISFET where the threshold voltage is high exist in the form of parallel connection. For this reason, in a wide-channel MISFET, e.g., one with a channel width of 10 &mgr;m, a hump characteristic curve indicated by a solid line in
FIG. 10
appears where that indicated by a broken line is to be obtained ideally. The hump characteristics are represented by two curve portions sandwiching a characteristic change point.
In a narrow-channel MISFET, e.g., one with a channel width of 0.2 &mgr;m, the channel planar portion has a width almost equal to the radius of curvature of the channel side edge portion. Thus, the gate electric field becomes almost equal between the channel side edge portion and the channel planar portion. In this case, the threshold voltage of the channel planar portion becomes equal to that of the drain current flowing through the channel side edge portion, inversion layers are formed in the channel side edge portion and channel planar portion simultaneously, and drain current starts to flow there. Therefore, the hump characteristics are not observed.
Appearance of the hump characteristics described in the above manner means that a subthreshold coefficient degrades in a wide-channel MISFET. In other words, the switching characteristics of the MISFET degrade. Due to the hump characteristics, upon application of a gate voltage equal to or lower than the threshold voltage, even when the gate voltage is kept unchanged, a subthreshold current larger than the ideal subthreshold characteristics by one or more orders of magnitudes flows. Therefore, if the MISFET is OFF, the power consumption increases.
Another problem arises as follows. When the channel width of the MISFET becomes 2 &mgr;m or less, the threshold voltage of the MISFET decreases greatly depending on the channel width, that is, a phenomenon called a reverse narrow channel effect occurs.
FIG. 9
shows the channel width dependence of the threshold voltage, i.e., so-called narrow channel characteristics, that occurs when the channels of the MISFETs are doped with an impurity of the same concentration. The reverse narrow channel effect appears in these narrow channel characteristics. As shown in
FIG. 9
, with the channel width of 2 &mgr;m or less, the threshold voltage varies depending on the channel width due to the reverse narrow channel effect. Therefore, in the semiconductor device described above with the wide- and narrow-channel MISFETs on the same substrate, the threshold voltage of the wide-channel MISFET and that of the narrow-channel MISFET differ from each other.
According to “TED Control Technology for Suppression of Reverse Narrow Channel Effect in 0.1 &mgr;m MOS Device”, Technical Digest of International Electron Device Meeting 1997, pp. 227-230, December 1997 (reference 1), during the manufacturing process for a MISFET with shallow trench isolation, transient enhanced diffusion causes redistribution of the channel impurity in the channel side edge portion. Hence, in a MISFET with a small channel width, the impurity concentration decreases over the entire channel when compared to that in a wide-channel MISFET.
When a MISFET with these characteristics is used in an integrated circuit, the following problems arise. For example, a static RAM with a CMOS cell structure is sometimes designed with a channel width of 0.3 &mgr;m or less to achieve a high integration degree. At this time, if the concentration of the channel impurity is set to match the threshold voltage of a wide-channel MISFET existing on the same substrate, sufficient cutoff
Fahmy Wael
NEC Corporation
Pham Hoai
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