Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including high voltage or high power devices isolated from...
Reexamination Certificate
2001-09-27
2003-01-14
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including high voltage or high power devices isolated from...
C257S501000, C257S506000, C257S481000, C257S603000
Reexamination Certificate
active
06507085
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and especially to a high voltage IC (hereinafter referred to as an “HVIC”) comprising a bootstrap diode.
2. Description of the Background Art
FIG. 29
is a circuit diagram of a conventional HVIC
110
and its peripheral circuits. As shown in
FIG. 29
, the conventional HVIC
110
comprises a bootstrap diode
102
and a logic circuit
103
formed in a high-potential island region
101
. In the periphery of the HVIC
110
, a bootstrap capacitance
200
is located in parallel with the logic circuit
103
. A cathode of the bootstrap diode
102
is connected to one end of the logic circuit
103
. A voltage source
150
L is connected to an anode of the bootstrap diode
102
.
Now, operations in the circuit diagram of
FIG. 29
will be set forth. When a voltage at the voltage source
150
L is higher than that at a virtual voltage source
150
H which is a virtual variable voltage source for determining a potential at the other end of the logic circuit
103
, the bootstrap diode
102
is forward biased and the voltage is supplied from the voltage source
150
L to the logic circuit
103
. At this time, an electric charge is applied to the bootstrap capacitance
200
and a potential at the cathode of the bootstrap diode
102
rises to (V
1
−Vrec), where Vrec is the forward voltage of the bootstrap diode
102
and V
1
is the voltage at the voltage source
150
L.
When, with the bootstrap capacitance
200
charged, the voltage at the virtual voltage source
150
H increases by &Dgr;V (>Vrec), the potential at the cathode of the bootstrap diode
102
becomes V
1
−Vrec+&Dgr;V (>V
1
). The bootstrap diode
102
is thus reverse biased and the current supply from the voltage source
150
L to the logic circuit
103
comes to a stop. At this time, the electric charge on the bootstrap capacitance
200
is supplied to the logic circuit
103
.
FIG. 30
is a schematic plan view of a configuration of the conventional HVIC
110
, and
FIG. 31
is a cross-sectional view taken along the line F—F indicated by the arrows. To avoid the complexity of the drawing, an insulating film
8
of
FIG. 31
is not shown in
FIG. 30
, which shows only a cathode and an anode electrodes
15
,
16
of the bootstrap diode
102
and a metal electrode
14
, out of the electrodes formed on an insulating film
18
. The conventional HVIC
110
utilizes a RESURF (reduced surface field) effect to provide isolation between the logic circuit
103
and the bootstrap diode
102
.
In the conventional HVIC
110
, as shown in
FIGS. 30 and 31
, an n
−
semiconductor layer
3
is formed on a p
−
semiconductor substrate
1
. An n
+
buried impurity region
2
is selectively formed at the interface between the p
−
semiconductor substrate
1
and the n
−
semiconductor layer
3
, and the logic circuit
103
is formed in the surface of the n
−
semiconductor layer
3
above the n
+
buried impurity region
2
. Near the end portion of the n
+
buried impurity region
2
, an n
+
impurity region
5
extending from the surface of the n
−
semiconductor layer
3
to the n
+
buried impurity region
2
is formed to surround the logic circuit
103
.
The n
+
impurity region
5
includes n
+
impurity regions
5
a
and
5
b
. The n
+
impurity region
5
a
is formed in the surface of the n
−
semiconductor layer
3
and connected to a metal electrode
55
which will be later described. The n
+
impurity region
5
b
is connected to the n
+
impurity region
5
a
and extends to the n
+
buried impurity region
2
.
On the side of the n
+
impurity region
5
opposite the logic circuit
103
, a p
+
impurity region
7
is formed in the surface of the n
−
semiconductor layer
3
, apart from the n
+
impurity region
5
, to surround the logic circuit
103
and the n
+
impurity region
5
. In the surface of the n
−
semiconductor layer
3
between the p
+
impurity region
7
and the n
+
impurity region
5
, an oxide film
12
is formed, on which an electrode
19
b
is formed. This electrode
19
b
forms a so-called “multiple field plate” for improved breakdown voltage.
The logic circuit
103
comprises, for example, a p-channel MOSFET
130
. The p-channel MOSFET
130
comprises a p
+
drain region
31
, a p
+
source region
32
, and a gate electrode
36
. The drain region
31
and the source region
32
are formed with predetermined spacing in the surface of the n
−
semiconductor layer
3
, and the gate electrode
36
is formed through a gate insulating film
34
on the n
−
semiconductor layer
3
between the drain and source regions
31
and
32
. Further in the surface of the n
−
semiconductor layer
3
, an n
+
impurity region
30
is formed adjacent to the drain region
31
with the oxide film
12
in between.
Apart from the buried impurity region
2
, a buried impurity region
28
is selectively formed at the interface between the p
−
semiconductor substrate
1
and the n
−
semiconductor layer
3
. Extending from this buried impurity region
28
to the surface of the n
−
semiconductor layer
3
, an n
+
impurity region
45
is formed which is a cathode region of the bootstrap diode
102
. The n
+
impurity region
45
includes n
+
impurity regions
45
a
and
45
b
. The n
+
impurity region
45
a
is formed in the surface of the n
−
semiconductor layer
3
and connected to the cathode electrode
15
which will be later described. The n
+
impurity region
45
b
is connected to the n
+
impurity region
45
a
and extends to the n
+
buried impurity region
28
.
A p
+
impurity region
6
, which is an anode region of the bootstrap diode
102
, is formed apart from the p
+
impurity region
7
in the surface of the n
−
semiconductor layer
3
to surround the n
+
impurity region
45
. In the surface of the n
−
semiconductor layer
3
between the n
+
impurity region
45
and the p
+
impurity region
6
, the oxide film
12
is formed, on which an electrode
19
a
is formed. This electrode
19
a
also forms a multiple field plate.
Between the p
+
impurity regions
6
and
7
, a p
+
impurity region
4
extending from the interface between the p
−
semiconductor substrate
1
and the n
−
semiconductor layer
3
to the surface of the n
−
semiconductor layer
3
is formed in connection only with the p
+
impurity region
7
. The p
+
impurity region
4
is formed to surround the n
+
impurity region
45
and the p
+
impurity region
6
and to surround the p
+
impurity region
7
, the n
+
impurity region
5
, and the logic circuit
103
. That is, the bootstrap diode
102
and the high-potential island region
101
are isolated by the p
+
impurity region
4
.
The insulating film
18
is formed to cover the n
−
semiconductor layer
3
, the oxide film
12
, the gate electrode
36
, and the electrodes
19
a
and
19
b
. Through the insulating film
18
, the anode electrode
16
is connected to the p
+
impurity region
6
, the cathode electrode
15
to the n
+
impurity region
45
, and the metal electrode
55
to the n
+
impurity region
5
. A metal electrode
35
is connected through the insulating film
18
to the drain region
31
, the source region
32
, the gate electrode
36
, and the n
+
impurity region
30
. The cathode electrode
15
is connected by the metal electrode
14
to the metal electrode
55
and further to the metal electrode
35
on the drain region
31
and the n
+
impurity region
30
. This provides connection for the cathode of the bootstrap diode
102
and the logic circuit
103
as shown in
FIG. 29. A
floating metal electrode
50
is located on the insulating film
18
above the electrode
19
a
and its capacitive coupl
Fenty Jesse A.
Jackson Jerome
Mitsubishi Denki & Kabushiki Kaisha
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