Semiconductor device comprising an interconnect structure...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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C257S635000, C257S650000, C257S774000

Reexamination Certificate

active

06917110

ABSTRACT:
A semiconductor device capable of inhibiting a conductive plug from increase of resistance or disconnection resulting from moisture discharged from a first insulator film while reducing the capacitance between adjacent first interconnection layers is obtained. This semiconductor device comprises a plurality of first interconnection layers formed on a semiconductor substrate at a prescribed interval, a first insulator film, formed to fill up the clearance between the plurality of first interconnection layers, having an opening reaching the first interconnection layers and a conductive plug charged in the opening of the first insulator film and formed to be in contact with the first interconnection layers. An impurity is selectively introduced into a first region of the first insulator film in the vicinity of contact surfaces between the first interconnection layers and the conductive plug, thereby selectively modifying the first region of the first insulator film.

REFERENCES:
patent: 3747203 (1973-07-01), Shannon
patent: 4668973 (1987-05-01), Dawson et al.
patent: 4676867 (1987-06-01), Elkins et al.
patent: 4775550 (1988-10-01), Chu et al.
patent: 4885262 (1989-12-01), Ting et al.
patent: 4920071 (1990-04-01), Thomas
patent: 4962052 (1990-10-01), Asayama et al.
patent: 4983546 (1991-01-01), Hyun et al.
patent: 4984055 (1991-01-01), Okumura et al.
patent: 5003062 (1991-03-01), Yen
patent: 5024723 (1991-06-01), Goesele et al.
patent: 5084412 (1992-01-01), Nakasaki
patent: 5087589 (1992-02-01), Chapman et al.
patent: 5108787 (1992-04-01), Hiraki et al.
patent: 5153680 (1992-10-01), Naito et al.
patent: 5166768 (1992-11-01), Ito
patent: 5186745 (1993-02-01), Maniar
patent: 5192697 (1993-03-01), Leong
patent: 5270259 (1993-12-01), Ito et al.
patent: 5310700 (1994-05-01), Lien et al.
patent: 5314843 (1994-05-01), Yu et al.
patent: 5321211 (1994-06-01), Haslam et al.
patent: 5341026 (1994-08-01), Harada et al.
patent: 5352630 (1994-10-01), Kim et al.
patent: 5373192 (1994-12-01), Eguchi
patent: 5387812 (1995-02-01), Forouhi et al.
patent: 5404046 (1995-04-01), Matsumoto et al.
patent: 5429990 (1995-07-01), Liu et al.
patent: 5459086 (1995-10-01), Yang
patent: 5468684 (1995-11-01), Yoshimori et al.
patent: 5479054 (1995-12-01), Tottori
patent: 5496776 (1996-03-01), Chien et al.
patent: 5514910 (1996-05-01), Koyama
patent: 5519254 (1996-05-01), Tabara
patent: 5523616 (1996-06-01), Den
patent: 5541445 (1996-07-01), Quellet
patent: 5549786 (1996-08-01), Jones et al.
patent: 5569618 (1996-10-01), Matsubara
patent: 5581101 (1996-12-01), Ning et al.
patent: 5607880 (1997-03-01), Suzuki et al.
patent: 5616513 (1997-04-01), Shepard
patent: 5665845 (1997-09-01), Allman
patent: 5674784 (1997-10-01), Jang et al.
patent: 5702568 (1997-12-01), Shin et al.
patent: 5723895 (1998-03-01), Takahashi
patent: 5753975 (1998-05-01), Matsuno
patent: 5786273 (1998-07-01), Hibi et al.
patent: 5817582 (1998-10-01), Maniar
patent: 5818068 (1998-10-01), Sasaki et al.
patent: 5830773 (1998-11-01), Brennan et al.
patent: 5855962 (1999-01-01), Cote et al.
patent: 5866476 (1999-02-01), Choi et al.
patent: 5892269 (1999-04-01), Inoue et al.
patent: 5898221 (1999-04-01), Mizuhara et al.
patent: 5930624 (1999-07-01), Murata et al.
patent: 5963827 (1999-10-01), Enomoto et al.
patent: 6001745 (1999-12-01), Tu et al.
patent: 6013578 (2000-01-01), Jun
patent: 6071807 (2000-06-01), Watanabe et al.
patent: 42 18 495 (1992-12-01), None
patent: 0 602 607 (1994-06-01), None
patent: 56-125844 (1981-10-01), None
patent: 58-31519 (1983-02-01), None
patent: 59-17243 (1984-01-01), None
patent: 62-60242 (1987-03-01), None
patent: 63-198359 (1988-08-01), None
patent: 1-199456 (1989-08-01), None
patent: 1-307247 (1989-12-01), None
patent: 1-319942 (1989-12-01), None
patent: 2-7451 (1990-01-01), None
patent: 2-26055 (1990-01-01), None
patent: 2-101532 (1990-04-01), None
patent: 2-235358 (1990-09-01), None
patent: 2-253643 (1990-10-01), None
patent: 3-101130 (1991-04-01), None
patent: 4-234149 (1992-08-01), None
patent: 4-307934 (1992-10-01), None
patent: 4-317358 (1992-11-01), None
patent: 5-74963 (1993-03-01), None
patent: 5-198523 (1993-08-01), None
patent: 5-226334 (1993-09-01), None
patent: 8-218284 (1994-08-01), None
patent: 6-275229 (1994-09-01), None
patent: 6-291202 (1994-10-01), None
patent: 6-349950 (1994-12-01), None
patent: 7-99195 (1995-04-01), None
patent: 8-17770 (1996-01-01), None
patent: 8-64561 (1996-03-01), None
patent: 8-241891 (1996-09-01), None
patent: 9-69562 (1997-03-01), None
patent: 9-246375 (1997-09-01), None
patent: 9-312339 (1997-12-01), None
patent: 9-330982 (1997-12-01), None
patent: 10-209147 (1998-08-01), None
patent: 10-270447 (1998-10-01), None
patent: 10270447 (1998-10-01), None
patent: 10-303295 (1998-11-01), None
patent: 11-162967 (1999-06-01), None
patent: 0179563 (1998-11-01), None
Wolf, S.; Silicon Processing for the VLSI Era; vol. 2, Lattice Press; pp. 232-233.
“Multilevel-Interconnect Technology for VLSI and ULSI” Stanley Wolf, Ph.D.Silicon Processing for the VLSI ERAvol. 2 -Process Integration (1990) pp. 201-204, 226-228, 232-233.
“Lithography I: Optical Resist Materials and Process Technology”Silicon Processing for the VLSI ERAvol. 1 -Process Technology (1986) p. 441.
“1995 Proceedings Twelfth International VLSI Multilevel Interconnection Conference (VMIC)” Library of Congress No. 89-644090 (Jun. 27-29, 1995) Santa Clara, CA, pp. 457-463.
“Si-SiO2MOS Diode” S.M. SzePhysics of Semiconductor Device2nd ed.(1981) p. 393.
“A Study of Plasma Treatments on Siloxane SOG” C.K. Wang, et al.IEEE VMIC Conference(Jun. 7-8, 1994) pp. 101-107.
“Defects Study on Spin on Glass Planarization Technology” C. Chiang, et al.IEEE VMIC Conference(Jun. 15-16, 1987) pp. 404-412.
“Fluorine-Implanted Treatment (FIT) SOG for the Non-Etchback Intermetal Dielectric” Lai-Juh Chen, et al.IEEE VMIC Conference(Jun. 7-8, 1994) pp. 81-86.
“Modification Effects in Ion-Implanted SiO2Spin-on-Glass” N. Moriya et al.J. Electrochem Soc.vol. 140, No. 5 (May 1993) pp. 1442-1450.
“An Advanced Interlayer Dielectric System with Partially Converted Organic SOG by Using Plasma Treatment” M. Matsuura et al.IEEE VMIC Conference(Jun. 8-9, 1993) pp. 113-115.
“Mechanism for AlSiCu Alloy Corrosion” Tomoaki Ishida et al.,Jpn. J. Appl. Phys.vol. 31 Part 1 No. 6B (Jun. 1992) pp. 2045-2048.
“Moisture-Blocking Mechanism of ECR-Plasma SiO2and High Reliable Performance of Multilevel-Al-Metalization” M. Doki et al.,IEEE VMIC Conference(Jun. 7-8, 1994) pp. 235-239.
“Dielectric Constant of Silicon Dioxide Deposited by Atmospheric-Pressure Chemical Vapor Deposition Using Tetraethylorthosilicate and Ozone” Katsumi Murase,Jpn. J. Appl. Phys.vol. 33 Part 1 No. 3A (Mar. 1994) pp. 1385-1389.
“Suppression of MOSFET Hot Carrier Degradation by P-SiO Underlayer” Kimiaki Shimokawa et al., Technical Report of IEICE SDM92-133 (Dec., 1992) pp. 89 (English abstract) pp. 90-94 (Japanese).

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