Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – With specified electrode means
Reexamination Certificate
1999-06-08
2001-03-06
Picardat, Kevin M. (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
With specified electrode means
C257S565000, C257S587000, C257S734000
Reexamination Certificate
active
06198155
ABSTRACT:
Semiconductor device comprising an integrated circuit provided with a ceramic security coating and method of manufacturing such a device.
The invention relates to a semiconductor device having a silicon substrate which is provided on a first side with semiconductor elements, a metallization with connection pads for external contact and a passivation layer which leaves the connection pads of the metallization exposed, said first side further being provided with a ceramic security coating which also leaves the connection pads of the metallization exposed. The invention also relates to a method of manufacturing such a semiconductor device.
The semiconductor elements and the metallization form an integrated circuit which can be externally contacted by means of the connection pads. The circuit is covered with a passivation layer which, in practice, is a layer of silicon oxide or silicon nitride.
The ceramic security coating serves to render the integrated circuit inaccessible. By virtue thereof, reverse engineering is precluded. It is also precluded that restricted information stored in the integrated circuit is easily accessible. The latter is important if the integrated circuit is used in “smart cards”, such as cash cards and credit cards. The protective layer should offer optical, physical and chemical protection. The layer must absorb, scatter or reflect radiation, visible light as well as UV, IR and electron radiation. The layer must be resistant to scratching and polishing. In addition, it must be impossible to remove the layer by etching without rendering the underlying circuit useless.
In U.S. Pat. No. 5,399,441 a description is given of a semiconductor device of the type mentioned in the opening paragraph, in which the ceramic security coating is a layer having a matrix of silicon oxide. This matrix is formed by heating a layer of a solution of a silicon-oxide monomer, such as hydrogen silsesqui oxane, in for example toluene. The monomer may also include organic side groups. The silicon oxide matrix is formed by heating at a temperature in the range between 50° C. and 800° C. In this manner, a porous ceramic layer is formed. To give the layer desired properties, particles of a filler may be incorporated in the matrix of silicon oxide. In this manner it is possible, for example, to render the layer opaque and provide the layer with a rough surface.
If the layer is used on an integrated circuit having a passivation layer of silicon nitride, then the protective layer must be very thick. The protective layer is porous, so that etch solutions can penetrate through the layer. The silicon oxide-containing protective layer may be etched away in etch baths, such as HF-containing baths, without seriously attacking the underlying silicon nitride layer. The selectivity with which silicon oxide can be etched in relation to silicon nitride is very high. Care must be taken that, before the protective layer is entirely etched away, the underlying silicon nitride layer has been removed and sufficient damage has been done to the underlying circuit. The protective layer having a matrix of silicon oxide must be provided in a thickness which is at least one hundred times the thickness of the passivation layer of silicon nitride. In practice, the passivation layer has a thickness of approximately 2 &mgr;m, so that the protective layer must have a thickness of at least 200 &mgr;m. If the integrated circuit is to be used in “smart cards”, said thickness of the protective layer is undesirable. In the case of integrated circuits for “smart cards”, the silicon substrate including semiconductor elements, metallization and passivation layers has a thickness of approximately 150 &mgr;m. The integrated circuit is incorporated in a plastic card having a thickness of approximately 500 &mgr;m. Preferably, the thickness of the security layer does not exceed 10 &mgr;m.
It is an object of the invention to provide a semiconductor device of the type mentioned in the opening paragraph, which semiconductor device has a relatively thin protective layer, so that it is more suitable for use in smart cards. To achieve this, this semiconductor device is characterized in that the ceramic security coating is a layer having a matrix of monoaluminium phosphate. Such a layer has a very great mechanical strength and is not attacked in customary etch baths. The layer can be readily provided in a thickness ranging from 2 to 10 &mgr;m. As a result, the thickness of the integrated circuit is increased only to a very small degree by the provision of this protective layer, so that the circuit can suitably be used in smart cards. The layer can be applied to customary passivation layers. In customary etch baths, the passivation layers, which are situated below the porous protective layer, are often attacked while the protective layer remains intact. Since the protective layer only has a small thickness, the provision of said layer causes only very small stresses in the silicon substrate, which do not adversely affect the operation of the integrated circuit.
To render the protective layer impervious to radiation as well, particles may be added to the layer which absorb or scatter said radiation. These particles may consist, for example, of aluminium oxide, zirconium oxide, silicon oxide, titanium oxide, zinc oxide, silicon carbide or titanium carbide. Preferably, titanium dioxide particles are incorporated in the matrix of monoaluminium phosphate. The particles added to the layer have a diameter of approximately 0.25 &mgr;m, and they render this layer impervious to radiation if only 65% by weight of these particles is added to the layer.
In a further embodiment of the semiconductor device in accordance with the invention, a top layer having a matrix of monoaluminium phosphate in which no particles are incorporated is provided on the ceramic layer having a matrix of monoaluminium phosphate in which titanium oxide particles are incorporated. Due to the addition of these particles, the layer with the titanium dioxide particles has a relatively rough surface. By providing the above-mentioned top layer on this surface, a flat is obtained. The layer containing titanium dioxide particles is planarized by the top layer. In addition, when the top layer is provided, it penetrates into the pores of the titanium dioxide-containing layer, thereby forming a dense, strong layer. The resultant denser layer also makes better contact with the passivation layer, so that the adhesion to the passivation layer is better too.
In the manufacture of the semiconductor device mentioned in the opening paragraph, the ceramic security coating is formed, in accordance with the invention, on the first side of the silicon substrate by depositing a layer of a solution of monoaluminium phosphate in water on this side and subsequently heating this layer to a temperature in the range from 250° C. to 450° C. During the thermal treatment, the monoaluminium phosphate matrix is formed. Titanium oxide particles may be added to the solution in the form of a powder and are incorporated in the matrix during the thermal treatment. The layer is formed in an environmentally friendly manner because in the formation of the layer, water is used as the solvent. As mentioned hereinabove, toluene is used as the solvent in the method known from U.S. Pat. No. 5,399,441.
Preferably, if the passivation layer is a layer of silicon nitride, said passivation layer is superficially oxidized in an ozone-containing atmosphere, prior to the deposition of the monoaluminium phosphate solution. By virtue thereof, the adhesion of the ceramic layer is improved. The monoaluminium phosphate matrix is chemically bonded to the surface of the passivation layer.
A further advantage of the method resides in that the layer with the monoaluminium phosphate solution can be readily selectively deposited on the first side of the silicon substrate by providing the layer with a hydrophobic surface at locations where said layer is not desired. The aqueous solution in which the monoaluminium phosphate layer is provi
Van Bommel Marcus J.
Van Lierop Joseph G.
Verhaegh Nijnke A. M.
Biren Steven R.
Collins D. M.
Picardat Kevin M.
U.S. Philips Corporation
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