Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Heterojunction formed between semiconductor materials which...
Reexamination Certificate
2001-12-20
2003-05-06
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Heterojunction formed between semiconductor materials which...
C257S200000, C257S209000, C438S128000
Reexamination Certificate
active
06559483
ABSTRACT:
The present invention relates to a semiconductor device comprising an arrangement of a non-volatile memory element.
Small-size programmable non-volatile memories are used in a plurality of microelectronic products, such as logic and analogue devices, for example to identify a die or a product. Other applications involve storage for e.g. security bits, electronic keys, network address bits, and low-density operating system codes.
Several methods of incorporating small-size programmable non-volatile memories in a semiconductor device are known: e.g. laser cutting of dedicated wiring patterns, application of single-poly (E)EPROMS, application of dedicated non-volatile devices like EPROM, EEPROM, or Flash-memory, and the application of fuse wires.
In general, these methods from the prior art are lacking in cost-effectiveness, reliability and scalability. For example, laser cutting may damage passivation layers in the semiconductor device. Moreover, laser cutting is a relatively slow process, which disadvantageously reduces the overall process throughput.
Application of dedicated non-volatile devices like EPROM, EEPROM, or Flash-memory requires many additional processing steps, which add to the cost of the product.
Single-poly (E)EPROMS require a lower tunnel oxide limit of approximately 7 nm, for proper data retention and low leakage currents. In deep sub-micron processes, for example 0.25 &mgr;m and below, the gate oxide is typically less than 7 nm. Thus, for (E)EPROMS additional processing steps are required which add to the manufacturing costs.
Finally, a fuse wire provides a relatively simple memory element which, during a programming step, can be written by joule heating induced by a current flow in the fuse wire. The fuse wire melts and disconnects during such a programming step.
However, the energy dissipation necessary to fuse a fuse wire may require a current flow that is too high to be provided through the fuse wire itself. From the prior art, it is known that programming of a fuse wire memory element can be improved by providing an additional heating wire, which is positioned close to the fuse wire, and which locally supplies additional heat to the fuse wire programmed by joule heating of such an additional heating wire.
U.S. Pat. No. 3,699,403 describes such heating wire elements in a matrix of diodes on a semiconductor surface. The heating wire elements are arranged as planar wires that provide additional heat to the diodes in the matrix. A diode is programmed by a current flow, whose energy dissipation in combination with the heat from the heating wire is sufficient to fuse the diode.
U.S. Pat. No. 4,814,853 discloses a semiconductor device with a programmable fuse, in which a planar heating wire is formed on a substrate. Separated by an insulation layer, a planar fuse wire is formed on top of the heating wire. The fuse wire extends in a direction perpendicular to the direction of the heating wire. Due to the crossing of the fuse wire and the heating wire, the additional heat generated by the heating wire affects the fuse wire only at the crossing, which results in a more reliable and better localized fusing process.
U.S. Pat. No. 5,444,287 describes a thermally activated noise immune fuse in a semiconductor device. This fuse comprises a fuse wire and a heating wire which are thermally coupled by a coupling layer. The coupling layer transfers the heat from the heating wire to the fuse wire during programming. The heating wire may run parallel to the fuse wire in the same plane. Also, the heating wire may cross the fuse wire in a plane below, or above the plane comprising the fuse wire. The arrangement of the fuse disclosed in U.S. Pat. No. 5,444,287 is less susceptible to inadvertent programming due to voltage spikes (noise) on one of the wires.
Difficulties regarding for reliable programming of fuse wires from the prior art arise when feature sizes are reduced to the (deep) sub-micron level. Since the supply voltage (V
cc
) in microelectronic devices scales down with the reduction in feature size, in the process generation of 0.25 &mgr;m the energy dissipation already becomes critical (with V
cc
=2.5 V). In future process generations below 0.25 &mgr;m, when the supply voltage is expected to reduce further, programming of fuse wire memory elements will become even more difficult. Moreover, since the overlapping area between the fuse wire and the heating wire becomes smaller due to the reduction of the line widths, the heat exchange area also becomes smaller, leading to relatively larger thermal losses and a lower efficiency.
It is an object of the present invention to provide a semiconductor device comprising an arrangement of an electrically programmable non-volatile memory element which may be operated at a low voltage.
The present invention relates to a semiconductor device comprising an arrangement of an electrically programmable non-volatile memory element, formed on a semiconductor surface, for storing a data bit; the non-volatile memory element comprising a fuse wire and a heating wire; the fuse wire being arranged as a planar line, and further being arranged as a memory element to be programmable by blowing the fuse wire through joule heating induced by a current flow; the heating wire being arranged to generate additional heat by current flow-induced joule heating and to provide said additional heat to the fuse wire during programming of the fuse wire;
characterized in that the heating wire is arranged as a heater spatially surrounding the fuse wire.
Also, the present invention relates to a semiconductor device comprising an arrangement of an electrically programmable non-volatile memory element, as described above, characterized in that the heating wire comprises horizontal wire parts and vertical wire parts; the horizontal wire parts and the vertical wire parts being arranged in a series connection to form the heating wire.
Moreover, the present invention relates to a semiconductor device comprising an arrangement of an electrically programmable non-volatile memory element as described above, characterized in that the horizontal wire parts are formed as horizontal lines in local interconnect and metallization layers of the semiconductor device, and
the vertical wire parts are being formed as vertical contacts and vias in the semiconductor device.
Furthermore, the present invention relates to a semiconductor device comprising an arrangement of an electrically programmable non-volatile memory element as described above, characterized in that the horizontal lines in local interconnect and metallization layers of the semiconductor device, and the vertical contacts and vias in the semiconductor device, are formed as sub-micron level parts of the semiconductor device.
If the non-volatile memory element comprises a metallization layer of the semiconductor device such as the first metallization layer known in the art as “Metal One”, the present invention also relates to a semiconductor device comprising an arrangement of an electrically programmable non-volatile memory element, characterized in that the fuse wire is formed in a metallization level layer of the semiconductor device.
And in that case, the present invention relates to a semiconductor device comprising an arrangement of an electrically programmable non-volatile memory element, characterized in that the heater spatially surrounding the fuse wire is arranged as a series of open loops around the fuse wire; the open loops twisting in a direction parallel to the fuse wire.
Alternatively, the fuse wire may be formed in the local interconnect layer of the semiconductor device. Then, the present invention also relates to a semiconductor device comprising an arrangement of an electrically programmable non-volatile memory element, characterized in that the fuse wire is formed in a local interconnect layer of the semiconductor device.
Furthermore, the present invention relates to a semiconductor device comprising an arrangement of an electrically programmable non-volatile memory element, characterized in
Koninklijke Philips Electronics , N.V.
Nguyen Thinh
Waxler Aaron
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