Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
1999-12-14
2001-06-12
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S737000, C257S692000, C257S693000, C257S676000, C257S698000, C257S780000, C257S208000, C257S210000
Reexamination Certificate
active
06246117
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the semiconductor device.
2. Description of the Related Art
A BGA (Ball-Grid-Array) type semiconductor package has been known as a semiconductor package for a semiconductor device.
Such the semiconductor device comprise a lead frame, a semiconductor chip, bonding wires, and solder balls.
The semiconductor chip is mounted on one side of the lead frame with wire bonding which establishes electrical connection. The solder balls are disposed on an underside portion of the lead frame at predetermined intervals, and act as connection terminals of the semiconductor device. The semiconductor chip and the bonding wires are encapsulated with a plastic (resin).
The solder balls are melted when the semiconductor device is mounted on a printed circuit board, thus the solder balls are connected to the printed circuit board. As a result, electrical connection between the semiconductor chip and the printed circuit board is established.
Conventionally, there are two typical ways to form a region (land) of the lead frame on which the solder balls are disposed as follows.
1) Half Etching (disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H9-246427): To etch regions, which do not correspond to portions to be the lands, on one side of the lead frame to predetermined depth (do not etch fully) to form the land portions. Then the semiconductor chip is mounted on the other side of the lead frame with wire bonding. The mounted chip and the bonding wires are encapsulated with a plastic. The encapsulant plastic also covers the half-etched portions, thus the lands are exposed. Finally, the solder balls are formed on the lands.
2) Limited Encapsulation (disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H10-84055): To encapsulate the semiconductor device wholly except regions to be the lands. More precisely, after the chip is mounted on the lead frame, the semiconductor device is subjected to encapsulation process with using a mold which has projected portions corresponding to the regions to be the lands. The semiconductor package is wholly encapsulated except the land regions by injecting an encapsulant plastic. Thus, the lands are exposed, and the solder balls are formed on the lands.
According to the first method, the lead frame is weakened because of the half etching. Therefore, jamming tends to occur during the manufacturing process. As a result, this method costs much because yield of the semiconductor device is poor.
The second method also has disadvantages. The available minimum intervals among the projected portions may be 0.6 mm. Therefore, this method is not suitable for manufacturing a semiconductor package in which lands are formed at intervals equal to or less than 0.6 mm. Moreover, various molds are required in accordance with various sizes of the solder balls, land intervals, and the like. This method also costs much.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device and a manufacturing method of the semiconductor device which save manufacturing costs. It is another object of the present invention to provide a manufacturing method of a semiconductor device with excellent yield. It is a further object of the present invention to provide a manufacturing method of a semiconductor device which flexibly corresponds to modification of connection terminals'intervals.
To accomplish the above objects, a semiconductor device according to a first aspect of the present invention is a semiconductor device comprises:
a lead frame;
a semiconductor chip mounted on one side of the lead frame;
wires which electrically interconnects the semiconductor chip and the lead frame;
an insulation film, formed on the other side of the lead frame, which has openings for exposing predetermined portions of the lead frame; and
connection terminals formed on the predetermined portions of the lead frame which are exposed by the insulation film.
According to the invention, the regions for the connection terminals are exposed through the openings in the insulation film. That is, the insulation film determines the regions. Therefore, the lead frame itself is not influenced at all for exposing the regions for forming the connection terminals because the lead frame is not processed. As a result, manufacturing of the semiconductor device with excellent yield is realized with low cost.
The insulation film may be affixed onto the other side of the lead frame.
Each of the openings in the insulation film may have diameter which is substantially the same as diameter of corresponding connection terminals.
The insulation film may have at least one of thermosetting property and thermo plasticity.
The connection terminals may be made of solder.
A manufacturing method of a semiconductor device according to the second aspect of the present invention is a method comprises:
preparing a lead frame;
mounting a semiconductor chip on one side of the lead frame;
electrically connecting the semiconductor chip and the lead frame by wires;
applying an insulation film, which has openings for exposing predetermined portions of the lead frame, onto the other side of the lead frame; and
forming connection terminals on the predetermined portions of the lead frame exposed through the openings in the insulation film.
The applying the insulation film may include affixing the insulation film onto the lead frame.
The applying the insulation film may include applying the insulation film having the openings each of whose diameter is substantially the same as diameter of corresponding connection terminal.
The applying the insulation film may include encapsulating the semiconductor chip and the wires with a plastic before applying the insulation film.
The forming the connection terminals may include forming the connection terminals made of solder.
REFERENCES:
patent: 5729051 (1998-03-01), Nakamura
patent: 5974912 (1999-11-01), Fukutami et al.
patent: 5999413 (1999-12-01), Ohuchi et al.
patent: 6011694 (2000-01-01), Hirakawa
patent: 6013953 (2000-01-01), Nishihara et al.
patent: 6020218 (2000-02-01), Shim et al.
patent: 6071755 (2000-06-01), Baha et al.
patent: 6084300 (2000-07-01), Oka
patent: 6097101 (2000-08-01), Sato et al.
patent: 9-246427 (1997-09-01), None
patent: 10-84055 (1998-03-01), None
NEC Corporation
Scully Scott Murphy & Presser
Williams Alexander O.
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