Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
2003-02-25
2004-05-18
Ngo, Ngan V (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S187000, C257S201000
Reexamination Certificate
active
06737683
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device composed of a group III-V nitride semiconductor represented by a general formula (In
X
Al
1-X
)
Y
Ga
1-Y
N (where 0≦X≦1 and 0≦Y≦1 are satisfied) and to a method for fabricating the same.
A group III-V nitride semiconductor such as GaN, AlGaN, InGaN, or InAlGaN, i.e., a so-called gallium nitride-based semiconductor is an important semiconductor for an optical device having a short oscillating wavelength such as a semiconductor laser device outputting, e.g., a blue laser beam. The applications of the gallium nitride-based semiconductor are not limited to the optical device. In recent years, attention has been focused on the gallium nitride-based semiconductor for its high dielectric breakdown field strength, high thermal conductivity, and high electron saturation velocity so that gallium nitride-based semiconductor is considered to be promising also as the material of an RF power device.
In an AlGaN/GaN heterojunction structure composed of aluminum gallium nitride (AlGaN) and gallium nitride (GaN) which are stacked in layers, in particular, electrons are accumulated at a high density in the vicinity of the heterojunction interface between AlGaN and GaN to form a so-called two-dimensional electron gas. The two-dimensional electron gas exhibits a high mobility since it exists spatially separated from a donor impurity used to dope AlGaN. Therefore, the AlGaN/GaN heterojunction structure achieves the effect of reducing a source resistance component when used in a field effect transistor (FET).
Since the distance d from a gate electrode to the two-dimensional gas is normally as small as several tens of nanometers, a ratio Lg/d between a gate length Lg and the distance d, which is termed an aspect ratio, can be held at a large value of 5 to 10 even if the gate length Lg is as small as about 100 nm. Hence, the use of the AlGaN/GaN heterojunction structure offers an advantage of easy fabrication of a FET with a reduced short channel effect and an excellent saturation characteristic.
The electron velocity of a two-dimensional electron in a high-field region of about 1×10
5
V/cm in the AlGaN/GaN-based heterojunction structure is double or more the electron velocity thereof in a gallium arsenide-based (GaAs-based) FET which is currently prevalent as an RF transistor, i.e., an AlGaAs/InGaAs heterostructure FET. In addition, the density of electrons accumulated at the heterointerface becomes as high as 1×10
13
/cm
2
when the composition of Al in AlGaN is 0.2 to 0.3, which is about three to five times as high as the density of electrons in the GaAs-based device. Accordingly, the FET having a GaN heterojunction structure is considered to be very promising.
However, the FET having a GaN heterojunction structure has the problem that it is difficult to form a gate electrode on the bottom surface of a recess provided in the upper semiconductor thereof, i.e., a so-called recessed gate structure.
The reasons for this is that AlGaN and GaN in, e.g., an AlGaN/GaN heterojunction structure have different lattice constants and therefore an upper semiconductor layer composed of AlGaN cannot be formed sufficiently thick on a lower semiconductor layer composed of GaN and that wet etching is difficult because AlGaN is a chemically extremely stable material. Accordingly, a conventional FET with a GaN-based heterojunction structure mostly has a structure in which ohmic electrodes as source/drain electrodes and a gate electrode are disposed on a principal surface of the upper semiconductor layer composed of AlGaN, not a recessed gate structure.
Thus, in the structure in which the individual electrodes are formed on the same surface, it is difficult to sufficiently reduce the value of a source-to-gate resistance so that excellent physical properties inherent to the materials composing the GaN-based heterojunction structure FET cannot be obtained.
Since the thickness of the upper semiconductor layer composed of AlGaN is particularly small between the gate and source, an electron density in the region lowers directly if a surface potential for electrons is increased by any factor in the fabrication process. No matter how intensively a gate voltage with a positive value is applied to the gate electrode, the electron density in a region under the gate electrode cannot be increased to a value not more than a maximum electron density determined in the region between the source and drain electrodes. The phenomenon in which the surface potential for electrons is increased by any factor in the fabrication process is fatal to the GaN-based heterojunction FET.
This raises a demand for a structure in which the thickness of the region of the upper semiconductor layer composed of AlGaN which is located between the source and drain is increased such that an electron density between the source and gate is not affected by a variation in surface potential, i.e., a recessed gate structure. However, the use of a recessed gate structure in a FET having a GaN-based heterojunction structure is technically difficult, as described above, so that it is necessary to minimize the surface potential between the source and drain.
SUMMARY OF THE INVENTION
The present invention has been achieved in view of the foregoing problems and it is therefore an object of the present invention to reduce a surface potential for electrons in a group III-V nitride semiconductor and thereby reduce a source resistance, improve a drain current value, and increase a drain breakdown voltage.
Specifically, a first method for fabricating a semiconductor device according to the present invention comprises the steps of: (a) exposing a surface of an active region composed of a group III-V nitride semiconductor to a plasma to reduce a surface potential for an electron in the active region; and (b) selectively forming an ohmic electrode and a gate electrode on the active region with the reduced surface potential.
Since the first method for fabricating a semiconductor device selectively forms the ohmic electrode and the gate electrode on the active region with the reduced surface potential, a source resistance is reduced and a transconductance is increased. This advantageously increases a drain current as well as a drain breakdown voltage.
In the first method for fabricating a semiconductor device, the step (a) is preferably performed under a pressure not more than 100 Pa.
A second method for fabricating a semiconductor device according to the present invention comprises the steps of: (a) selectively forming an ohmic electrode and a gate electrode on an active region composed of a group III-V nitride semiconductor; and (b) exposing the active region to a plasma by using the ohmic electrode and the gate electrode as a mask to reduce a surface potential for an electron in an exposed region of the active region.
In the first method for fabricating a semiconductor device, the step (b) is preferably performed under a pressure not more than 100 Pa.
A first semiconductor device according to the present invention comprises: an active region composed of a group III-V nitride semiconductor; and a gate electrode formed on the active region and source and drain electrodes each formed in spaced apart relation to the gate electrode, a portion of the active region interposed between the gate electrode and the source electrode having a surface thereof exposed selectively to a plasma such that a surface potential for an electron is lower therein than in the other portion of the active region.
In the first semiconductor device, a source resistance is reduced and a transconductance is increased so that a drain current is increased advantageously.
In the first semiconductor device, it is preferable for a portion of the active region interposed between the gate electrode and the drain electrode also to have a surface thereof exposed selectively to the plasma such that a surface potential for an electron is lower therein than in the other portion of the active region.
This also reduc
Hirose Yutaka
Ikeda Yoshito
Inoue Kaoru
Nishii Katsunori
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Ngo Ngan V
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