Semiconductor device carrying a plurality of circuits

Details Semiconductor device carrying a plurality of circuits Semiconductor device carrying a plurality of circuits

2002-02-11

2004-07-13

Tran, Minhloan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular chip input/output means

C257S204000, C257S209000, C257S529000, C327S525000

Reexamination Certificate

active

06762442

ABSTRACT:

CROSS REFERENCES TO RELATED APPLICATIONS
The present invention claims priority to priority document no. 2001-036757 filed in Japan on Feb. 14, 2001, and incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device that has a plurality of circuits mounted on one chip and each of the circuits having the same or different function.
2. Description of the Related Art
As shown in
FIG. 5
, a semiconductor chip
20
forming part of a semiconductor device is broadly divided into an active region
21
which is a region for embodying functions as a circuit, and an I/O (Input/Output) region
23
provided with input terminals and output terminals required for interfacing the circuit with an external circuit.
The I/O region
23
is formed in the periphery of the semiconductor chip
20
, where a plurality of input/output pads
22
are provided as electrodes for connecting lead-out terminals for an LSI (Large Scale Integration) with the circuit inside the semiconductor chip through bonding wires.
Each of the input/output pads
22
is typically square shaped having sides approximately 100 &mgr;m in length. Due to limitations of mechanical accuracy of a bonding apparatus for use in a wire bonding process, it is difficult to significantly reduce the input/output pads
22
in size. Thus, when the required number of input/output pads
22
are arranged in the periphery of the rectangular chip
20
as shown in
FIG. 5
, the minimum chip size is accordingly determined.
In the chip sized as described above, the active region
21
surrounded by the I/O region
23
is a region where circuits can be actually placed. When circuits designed to fit in the active region
21
are placed, the circuits are formed aver the entire active region
21
.
With an increasingly miniaturized LSI, a higher speed processing ability, and realization of an extremely large-scale integrated circuit in a very limited area on a chip, however, the overall active region
21
may not be filled with circuits. In this case, the active region
21
includes a no-patterned region which has no circuit mounted therein. A no-patterned region may also occur for circuits that involve relatively simple signal processing and uses a small number of gates.
On the other hand, the size of the active region
21
is inevitably determined by the number of the input/output pads
22
and the size thereof, i.e. pad size. Since improvement in mechanical accuracy of a bonding apparatus does not catch up with improvement in integration degree, it is impossible to reduce the size of the active region
21
according to the scale of the mounted circuits.
For circuits that do not require high speed processing, occurrence of a no-patterned region can be avoided by lowering its integration degree. For circuits that require high speed processing, however, a higher integration degree (miniaturization) is needed, and in this case, design must be performed in preparation for occurrence of a no-patterned region. In addition, when a no-patterned region occurs, a problem of too much waste arises since the no-patterned region cannot be effectively utilized.
In this manner, in a conventional LSI, since the minimum chip size is inevitably determined by the number and size of the input/output pads, a problem of a no-patterned region created in an active region surrounded by an I/O region arises in a highly integrated circuit or a circuit with a small number of gates. Thus, there are challenges of solving such a problem and improving the yield of a semiconductor device.
SUMMARY OF THE INVENTION
The present invention provides, as a specific means for addressing the aforementioned challenges, a semiconductor device comprising on the same chip at least an I/O region where an input/output pad is formed and an active region where a plurality of circuits can be mounted, wherein a plurality of logic circuits having the same functions or different functions are mounted in the active region on the same chip.
In the semiconductor device thus configured, a no-patterned region having no circuit mounted therein is utilized in the active region where circuits can be mounted, and a plurality of logic circuits having functions identical to or different from those of logic circuits mounted in the remaining active region are mounted in the no-patterned region. Consequently, the device can be shipped as a product if at least one of the logic circuits operates normally to significantly improve and more effectively utilize the semiconductor device.
In addition, when the plurality of mounted circuits are different from one other and if some of the circuits do not operate normally, the device can be delivered as an LSI having the functions of the other circuits operating normally. If all the circuits operate normally, the device can be delivered as one product having different functions to provide various applications.
Furthermore, when the plurality of circuits have the same functions and all of them operate normally, the device can be delivered as a semiconductor product having a plurality of logic circuits with the same functions mounted thereon, and thus all the circuits can be effectively utilized with appropriate design of peripheral circuits.


REFERENCES:
patent: 5566107 (1996-10-01), Gilliam
patent: 5867691 (1999-02-01), Shiraishi
patent: 6446249 (2002-09-01), Wang et al.
patent: 2001-168284 (2001-06-01), None

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