Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2001-07-18
2003-11-18
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S107000, C702S118000, C702S120000
Reexamination Certificate
active
06651022
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and particularly, to a circuit for setting, to a test mode, a semiconductor circuit device capable of a test mode operation. More specifically, the present invention is related to a test mode setting circuit of such a semiconductor memory device.
2. Description of the Background Art
In a semiconductor integrated circuit device such as a dynamic random access memory (DRAM), in general, in the manufacturing process, tests are performed for checking whether normal operation can be implemented or not. Such tests include a screening test (burn-in test) for revealing a latent defect, a margin test for detecting margin defect of voltage or signal timing, and others. In such tests, a special chip operation (operation of a semiconductor integrated circuit device) that is not used in an actual use is performed, such that the semiconductor integrated circuit device is operated under a condition of high temperature and high voltage, or at a timing different from a normal operating timing. Such special chip operation is enabled by setting a test mode.
FIG. 8
is a schematic representation of an overall arrangement of a DRAM as an example of a conventional semiconductor integrated circuit device. In
FIG. 8
, a DRAM
100
includes a memory cell array
101
having memory cells MC arranged in a matrix of rows and columns, a word line WL provided corresponding to a row of memory cells, and a bit line BL disposed corresponding to a column of memory cells MC; a row decoder
102
for driving, to a selected state, a word line corresponding to an addressed row in memory cell array
101
according to an applied X signal; a sense amplifier
103
for sensing, amplifying and latching data of memory cells connected to a selected row; a column decoder
104
for selecting an addressed column of memory cell array
101
according to an applied Y signal.
DRAM
100
further includes a /RAS buffer
105
for taking in an externally applied row address strobe signal /RAS in synchronization with an internal clock signal CLK to generate internal signals ZRASE and int.RAS; a /CAS buffer
106
for taking in a column address strobe signal /CAS applied from an outside in synchronization with internal clock signal CLK to generate an internal column address strobe signal int.CAS; a /WE buffer
107
for taking in a write enable signal /WE applied from an outside in synchronization with internal clock signal CLK to generate an internal write enable signal int.WE; a row address buffer
108
for taking in an externally applied address in synchronization with an internal clock signal; a column address buffer
109
for taking in an externally applied address in synchronization with the internal clock signal; a row-related control circuit
110
for generating an X address according to an address signal from row address buffer
108
in response to activation of a row-related activation signal ZRASE from /RAS buffer
105
; a column-related control circuit
111
for generating a Y address according to an address signal from column address buffer
109
upon activation of a column select activation signal (only the path is shown) from /CAS buffer
106
; a write control circuit
112
for generating a write/read control signal according to a write/read instruction signal (only the path is shown) from /WE buffer
107
; and an input/output circuit
113
for inputting and outputting data between an internal data line I/O and the outside according to the write/read control signal from write control circuit
112
.
The column select activation signal is generated according to internal column address signal int.CAS, while the write/read control signal is generated according to internal write enable signal /WE.
A column select circuit that connects, to an internal data line I/O, a bit line corresponding to a selected column of memory cell array
101
according to a column select signal from column decoder
104
is arranged adjacent to sense amplifier
103
. The column select circuit, however, is not shown in the drawing for simplicity purpose.
Input/output circuit
113
includes a preamplifier
113
a
for amplifying data on internal data line I/O when activated, an output buffer
113
b
for buffering internal data amplified by preamplifier
113
a
to generate external read data DQ in a data read mode, an input buffer
113
d
for buffering write data DQ received from an outside in data write operation, and a write driver
113
c
activated according to the write/read control signal from write control circuit
112
for driving an internal data line I/O according to write data from input buffer
113
d.
DRAM
100
further includes an internal voltage generating circuit
114
for generating internal voltages Vdd, Vbb, and Vcp according to an externally applied external power-supply voltage or an internally generated internal power-supply voltage, a clock buffer
115
for buffering a clock signal ext.CLK applied from an outside to generate an internal clock signal CLK, and a mode setting circuit
120
for generating a mode setting signal TM for designating a specific operation mode according to internal control signals int.RAS, int.CAS, and int.WE from buffers
105
to
107
and an external address signal bit.
Voltage Vdd is an internal power-supply voltage generated by down-converting an external power-supply voltage in internal voltage generating circuit
114
. Voltage Vbb is a negative voltage generated through a charge pump operation in internal voltage generating circuit
114
, and is applied to a substrate region of memory cell array
101
and other. Voltage Vcp is a voltage applied to a cell plate of a capacitor included in a memory cell MC. Internal voltage generating circuit
114
further generates a bit line equalizing voltage Vb1 for precharging a bit line BL in a standby cycle, a high voltage Vpp transmitted on a selected word line WL, and such.
Mode setting circuit
120
determines that a special mode is designated when internal control signals int.RAS, int.CAS, and int.WE and a specific external address signal bit satisfy a prescribed condition, and generates a mode setting signal TM for performing a designated mode. Mode setting circuit
120
contains a mode register for setting an operation condition (burst length, CAS latency, and the like) of DRAM
100
.
In DRAM
100
as shown in
FIG. 8
, with mode setting circuit
120
, a burn-in test mode is set up when a burn-in test which is one of the screening tests is to be performed. In the burn-in test mode, the voltage levels of internal power-supply voltage Vdd, a cell plate voltage Vcp, a high voltage Vpp (not shown), a bit line precharge voltage Vb1 and other from internal voltage generating circuit
114
are set higher than the respective voltage levels under normal operation conditions, in order to accelerate voltage stress. Moreover, in such burn-in test, more word lines than those selected in a normal operation mode are selected simultaneously in memory cell array
101
.
Setting of these voltage conditions and setting of selecting conditions of word lines are performed individually using a specific set of externally applied address bits (address key).
FIG. 9
is a schematic representation of an arrangement of mode setting circuit
120
shown in FIG.
8
. In
FIG. 9
, mode setting circuit
120
includes a level detection circuit
121
for detecting whether a signal BA
0
of a specific node is set to a prescribed voltage condition; an MRS detection circuit
122
for detecting whether internal control signals int.RAS, int.CAS, int.WE satisfy a predetermined condition such as a WCBR (WE, CAS before RAS) condition; an address key detection circuit
123
for detecting whether a prescribed set of externally applied address signal bits A
0
to An satisfy a prescribed state; and a mode detection circuit
124
for activating a test mode instruction signal TEM when an output signal BA
0
S from level detection circuit
121
, an output signal MRS from MRS detection circuit
122
, a
Hoff Marc S.
McDermott & Will & Emery
Suarez Felix
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