Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2001-03-30
2002-12-17
Eckert, II, George C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S372000, C257S374000, C257S503000, C257S903000
Reexamination Certificate
active
06495899
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device such as a CMOS-type static random access memory (SRAM) device.
2. Description of the Related Art
Generally, one SRAM cell uses a flip-flop constructed by two cross-coupled inverters and two transfer transistors. In this case, each of the inverters has a load element and a drive transistor.
In view of the power consumption, a CMOS-type SRAM cell has been developed where the above-mentioned load element is constructed by a P-channel MOS transistor, while the above-mentioned drive transistor is constructed by an N-channel MOS transistor. This will be explained later in detail.
In the prior art CMOS-type SRAM cell, however, since the voltage at a well is not surely fixed to a definite voltage within the cell, a latch-up phenomenon may occur. In order to suppress or avoid such a latch-up phenomenon, the P-type impurity regions of an N-type well have to be sufficiently separated from the N-type impurity regions of a P-type well, which would reduce the integration density.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide. a semiconductor device such as a CMOS-type SRAM device capable of suppressing or avoiding a latch-up phenomenon.
According to the present invention, in a semiconductor device including a semiconductor substrate, a well formed on the semiconductor substrate, and a thick field insulating layer for surrounding an active area of the well, a contact structure is buried in a contact hole provided in the thick field insulating layer and is connected to the well, so as to fix a voltage at the well.
REFERENCES:
patent: 5200639 (1993-04-01), Ishizuka et al.
patent: 5453640 (1995-09-01), Kinoshita
patent: 5459346 (1995-10-01), Asakawa et al.
patent: 5594270 (1997-01-01), Hiramoto et al.
patent: 5889314 (1999-03-01), Hirabayashi
patent: 5896313 (1999-04-01), Kao et al.
patent: 6215155 (2001-04-01), Wollesen
patent: 6252294 (2001-06-01), Hattori et al.
patent: 6277708 (2001-08-01), Bothra et al.
High Density Thin Film Transistor Load SRAM Cell Using Trench DRAM Technology, Sep. 1993, IBM Technical Disclosure Bulletin, vol. No. 36, Issue No. 9A, TDB-ACC-NO: NA9309581, pp. 581-582.*
Chuang, Dah-zen,VLSI, 1995, p. 461.
Sedra and Smith,Microelectronic Circuits, 1987, p. 374.
Eckert II George C.
Foley & Lardner
NEC Corporation
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