Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
1999-09-17
2002-07-02
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S751000, C257S774000
Reexamination Certificate
active
06414395
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device, and more specifically, it relates to a semiconductor device improved to be capable of preventing disconnection in a through hole. The present invention also relates to a method of fabricating such a semiconductor device. The present invention further relates to an apparatus for fabricating such a semiconductor device.
2. Description of the Prior Art
FIG. 14
is a sectional view showing a part of a conventional integrated circuit provided with wires.
Referring to
FIG. 14
, a lower aluminum wire
2
is formed on an interlayer isolation film
20
provided on a semiconductor substrate
22
. Another interlayer isolation film
3
is formed on the interlayer isolation film
20
, to cover the aluminum wire
2
. A through hole
21
for partially exposing a surface of the aluminum wire
2
is formed in the interlayer isolation film
3
. An upper aluminum wire
1
, connected with the lower aluminum wire
2
through the through hole
21
, is provided on the interlayer isolation film
3
. In other words, the lower aluminum wire
2
is connected with the upper aluminum wire
1
through the through hole
21
. In the portion of the through hole
21
, the upper aluminum wire
1
is generally formed by a laminate of a barrier metal film and an aluminum wire.
A method of fabricating the conventional integrated circuit connecting the upper and lower wires through the through hole is now described.
Referring to
FIG. 15
, the lower aluminum wire
2
provided with an antireflection film
5
thereon is formed on the interlayer isolation film
20
. The interlayer isolation film
3
is formed on the interlayer isolation film
20
, to cover the aluminum wire
2
. A resist pattern
4
having an opening
4
a
in a portion for forming the through hole
21
is formed on the interlayer isolation film
3
.
Referring to
FIGS. 15 and 16
, the interlayer isolation film
3
is etched through the resist pattern
4
serving as a mask, for forming the through hole
21
partially exposing the surface of the aluminum wire
3
in the interlayer isolation film
3
. At this time, an inner edge
5
a
of the antireflection film
5
horizontally extends in the through hole
21
.
Referring to
FIGS. 17 and 18
, the surface of the aluminum wire
2
is etched by sputtering with Ar
+
, to be cleaned. Thereafter a barrier metal layer
7
is formed to cover an inner wall of the through hole
21
.
Referring to
FIG. 19
, the upper aluminum wire
8
connected with the lower aluminum wire
2
is formed through the through hole
21
.
The conventional method of fabricating a semiconductor device provided with multilayer wires, carried out in the aforementioned manner, has the following problem:
Referring to
FIG. 19
, the inner edge
5
a
of the antireflection film
5
horizontally extends in the through hole
21
, to define a clearance under the inner edge
5
a
. Thus, the upper aluminum wire
8
cannot fill up the clearance and is hence disadvantageously disconnected.
SUMMARY OF THE INVENTION
The present invention has been proposed in order to solve the aforementioned problem, and an object thereof is to provide a method of fabricating a semiconductor device, which is so improved that an upper wire is not disconnected in a through hole portion.
Another object of the present invention is to provide a semiconductor device obtained by such a fabrication method.
Still another object of the present invention is to provide a fabrication apparatus capable of implementing such a method of fabricating a semiconductor device.
A semiconductor device according to a first aspect of the present invention comprises a semiconductor substrate. A first wiring layer having an antireflection film thereon is provided on the semiconductor substrate. An interlayer isolation film is provided on the semiconductor substrate, to cover the first wiling layer. A through hole partially exposing a surface of the first wiring layer passes through the interlayer isolation film and the antireflection film. An inner edge of the antireflection film horizontally extends in the through hole. The semiconductor device further comprises a clearance filling member filling up a clearance under the inner edge and a barrier metal film continuously covering the exposed surface of the first wiring layer, an inner wall surface of the through hole and a surface of the interlayer isolation film. Passing through the through hole, a second wiring layer is provided on the interlayer isolation film to be connected with the first wiring layer through the barrier metal film.
According to this aspect, the clearance filling member fills up the clearance under the inner edge of the antireflection film, whereby the second wiring layer is embedded in the through hole without disconnection and connected with the first wiring layer.
In a semiconductor device according to a second aspect of the present invention, the clearance filling member is made of a material obtained by etching the inner wall surface of the through hole and the exposed surface of the first wiling layer, including a surface of the semiconductor substrate, by sputtering.
According to this aspect, the clearance filling member is made of the material obtained by etching the surface of the semiconductor substrate by sputtering, whereby the clearance can be readily filled up.
In a semiconductor device according to a third aspect of the present invention, the clearance filling member is formed by bulging the exposed surface of the first wiring layer.
According to this aspect, the clearance filling member, which is formed by bulging the surface of the first wiring layer, can be readily formed.
In a method of fabricating a semiconductor device according to a fourth aspect of the present invention, a first wiring layer provided with an antireflection film thereon is formed on a semiconductor substrate. An interlayer isolation film is formed on the semiconductor substrate, to cover the first wiring layer. A through hole passing through the interlayer isolation film and the antireflection film and partially exposing a surface of the first wiring layer is formed. A clearance under an inner edge of the antireflection film defined in formation of the through hole is filled up with a filler. The exposed surface of the first wiring layer, an inner wall surface of the through hole and a surface of the interlayer isolation film are continuously covered with a barrier metal film. Passing through the through hole, a second wiring layer is formed on the interlayer isolation film to be connected with the first wiring layer through the barrier metal film.
According to this aspect, the clearance under the inner edge of the antireflection film defined in formation of the through hole is filled up with the filler, whereby the second wiling layer can be connected with the first wiring layer without disconnection.
In a method of fabricating a semiconductor device according to a fifth aspect of the present invention, the step of filling up the clearance under the inner edge with the filler includes first and second sputter-etching steps of etching a surface (including a bottom portion and a side wall surface of the through hole) of the semiconductor substrate by sputtering thereby forming a side wall spacer on the inner wall of the through hole and etching the bottom portion of the through hole by sputtering thereby cleaning the surface of the first wiring layer.
According to this aspect, the clearance under the inner edge is filled up by etching the surface of the semiconductor substrate by sputtering thereby forming the side wall spacer on the inner wall of the through hole.
In a method of fabricating a semiconductor device according to a sixth aspect of the present invention, the first sputter-etching step is carried out under a high pressure of 1 to 20 mTorr, and the second sputter-etching step is carried out under a low pressure of 0.1 to 5 mTorr.
According to this aspect, the first sputter-etching step is carried out un
Hagi Kimio
Ookuma Yuuko
Loke Steven
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Vu Hung Kim
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