Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-10-31
2002-08-06
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S390000, C327S537000
Reexamination Certificate
active
06429724
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a charge pump circuit generating a boosted potential or a negative potential from a power supply potential supplied from the exterior and a nonvolatile semiconductor memory device comprising the same.
2. Description of the Prior Art
A semiconductor device such as a flash memory electrically writing, reading or erasing data generates a plurality of potentials in its interior in addition to a power supply potential which is supplied from the exterior, for writing, reading or erasing data through these potentials.
In the flash memory, for example, each memory cell is formed by a single transistor having a drain and a control gate which are connected to a bit line and a word line respectively. The flash memory erases data by applying a positive high potential to the control gate of the transistor forming the memory cell while applying a negative high potential to the source and a P well thereby injecting electrons into a floating gate through the F-N (Fowler-Nordheim) tunnel effect.
On the other hand, the flash memory writes data by applying a negative high potential to the control gate while applying a positive high potential to the drain thereby extracting electrons from the floating gate through the tunnel effect.
Internal potentials employed in respective operations of a conventional flash memory are now described.
FIGS. 44A and 44B
are adapted to illustrate potentials supplied to each memory cell of the conventional flash memory in respective modes.
In an erase operation for a selected block, a source potential Vs, a control gate potential Vcg and a potential BG of a well part (hereinafter referred to as a back gate) forming a channel of a transistor are −11 V, 12 V and −11 V respectively, and a drain potential Vd is in a floating state (Z) as shown in
FIGS. 44A and 44B
.
In a write operation for the selected block, the source potential Vs is in a floating state (Z), and the control gate potential Vcg, the back gate potential BG and the drain potential Vd are −11 V, 0 V and 5 to 9 V (set in units of 0.3 V) respectively.
In an OP (over-program) recovery operation for returning a threshold value into a normal range for recovering the selected block from an overwritten state, the source potential Vs, the control gate potential Vcg, the back gate potential BG and the drain potential Vd are 0 V, 6 V, 0 V and 8 V respectively.
In a read operation for the selected block, the source potential Vs, the control gate potential Vcg, the back gate potential BG and the drain potential Vd are 0 V, 3 V, 0 V and less than 1 V respectively.
When a power supply potential which is supplied from the exterior is only 3 V, therefore, the flash memory generally comprises a plurality of positive and negative potential generation circuits containing charge pump circuits therein, in order to generate the potentials of 12 V, 5 to 9 V, 8 V, 6 V and −11 V through the power supply potential respectively.
FIG. 45
is adapted to illustrate potentials generated by the charge pump circuits in the respective modes of the conventional flash memory.
Referring to
FIG. 45
, the conventional flash memory comprises three positive potential generation charge pump circuits generating positive potentials VPL, VPM and VPS respectively and a negative potential generation charge pump circuit generating a negative potential VN.
In case of erasing data in any memory cell, the positive and negative potentials VPL and VN are 12 V and −11 V respectively, while the positive potentials VPM and VPS are not used. The positive potential VPL is supplied to a selected word line. The negative potential VN is supplied to a well formed with a memory cell transistor and the source of the memory cell transistor.
In case of writing data in any memory cell, the positive potentials VPL and VPM are 12 V and 5 to 9 V respectively, and the negative potential VN is −11 V, while the positive potential VPS is not used. The positive potentials VPL and VPM and the negative potential VN are supplied to a selected selector gate line, a selected main bit line and a word line of a memory transistor respectively.
In OP recovery, the positive potentials VPL, VPM and VPS are 12 V, 8 V and 6 V respectively, while the negative potential VN is not used. The positive potentials VPL, VPM and VPS are supplied to a selected selector gate line, a selected main bit line and a word line of a memory transistor respectively.
As understood from the above description, the positive potential VPS and the negative potential VN are not simultaneously required in any operation. If a single circuit is servable both as the positive and negative potential generation charge pump circuits for generating the positive potential VPS and the negative potential VN, therefore, the area for a single charge pump circuit can be reduced.
FIG. 46
is a circuit diagram showing the structure of a conventional charge pump circuit for generating positive and negative potentials disclosed in Japanese Patent Laying-Open No. 7-177729 (1995).
Referring to
FIG. 46
, the conventional charge pump circuit for generating positive and negative potentials includes a P-channel MOS transistor
816
, receiving a control signal P-IN in its gate, which is connected between a power supply potential Vcc and a node L, a diode
801
having an anode and a cathode which are connected to the node L and a node A respectively, a diode
802
having an anode and a cathode which are connected to the node A and a node B respectively, a diode
803
having an anode and a cathode which are connected to the node B and a node C respectively, a diode
804
having an anode and a cathode which are connected to the node C and a node D respectively, a diode
805
having an anode and a cathode which are connected to the node D and a node E respectively, a diode
806
having an anode and a cathode which are connected to the node E and a node F respectively, a diode
807
having an anode and a cathode which are connected to the node F and a node M respectively, and an N-channel MOS transistor
817
, receiving a control signal N-IN in its gate, which is connected between a ground potential GND and the node M.
The conventional charge pump circuit for generating positive and negative potentials further includes a capacitor
840
connected between a clock node which is supplied with a clock signal PH and the node A, a capacitor
841
connected between a complementary clock node which is supplied with a clock signal /PH, complementary to the clock signal PH, and the node B, a capacitor
842
connected between the clock node and the node C, a capacitor
843
connected between the complementary clock node and the node D, a capacitor
844
connected between the clock node and the node E, and a capacitor
845
connected between the complementary clock node and the node F.
Operations of the conventional charge pump circuit for generating positive and negative potentials are now briefly described.
In case of generating a positive potential VHP, the control signal P-IN is activated and the P-channel MOS transistor
816
conducts to supply the power supply potential Vcc to the node L. On the other hand, the control signal N-IN is inactivated and the N-channel MOS transistor
817
enters a non-conducting state. A voltage responsive to the amplitude of the clock signals PH and /PH and the stage number of the diodes
801
to
807
is generated by a charge pump operation to cause a constant potential difference between the nodes L and M. Since the node L is supplied with the power supply potential Vcc, the potential of the node M reaches a constant level which is higher than the power supply potential Vcc, to provide the positive potential VHP.
In case of generating a negative potential VHN, on the other hand, the control signal N-IN is activated and the N-channel MOS transistor
817
conducts to supply the ground potential GND to the node M. On the other hand, the con
Mihara Masaaki
Ogura Taku
Callahan Timothy P.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Hai L.
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