Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2002-07-24
2004-03-23
Nguyen, Van Thu (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S685000, C257S678000, C257S673000, C257S689000, C257S692000, C257S723000, C257S698000
Reexamination Certificate
active
06710435
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an arrangement of semiconductor devices. In addition, this invention relates to a method of fabricating a semiconductor device arrangement.
2. Description of the Related Art
Japanese patent application publication number 7-86493 discloses a multi-chip module including a three-dimensional glass substrate having the shape of a cube or a rectangular parallelepiped. The three-dimensional glass substrate is mounted on a main substrate. One of the surfaces of the three-dimensional glass substrate contacts with the main substrate. Wiring lines, bare LSI chips, resistors, and capacitors are formed and mounted on the other surfaces of the three-dimensional glass substrate by a sequence of steps. The total number of the steps tends to be relatively large.
Japanese patent application publication number 6-5665 discloses that holes are formed in a surface of an IC wafer at positions on cutting lines, and electrodes are provided in the holes respectively. The formation of the holes uses, for example, wet etching or dry etching. The holes are of the through type or the recess type. After the electrodes are provided, the IC wafer is cut along the cutting lines so that IC chips are made. Electrodes are exposed at the side surfaces of each IC chip. Plural IC chips can be superposed while being aligned. Electrical connections among the IC chips in the superposition can easily be provided by use of the electrodes at the side surfaces of the IC chips. The total number of the holes in the IC wafer tends to be relatively large. In the case where the holes are formed in the IC wafer by wet etching or dry etching after IC patterns are provided thereon, particles tend to cause pinholes in the IC wafer and also breaks of wiring lines thereon.
Japanese patent application publication number P2000-101020A discloses a semiconductor chip having plural surfaces which are provided with semiconductor devices respectively. The semiconductor chip is fabricated as follows. An array of first LSI's (semiconductor devices) is formed on an upper surface of a silicon wafer. Then, the silicon wafer is cut into sample blocks by a scribing procedure or a dicing procedure using one, of a diamond blade and a wire saw. The sample blocks have first surfaces provided with the first LSI's respectively. The sample blocks are rearranged into a pseudo wafer having an upper surface formed by second surfaces of the sample blocks. An array of second LSI's (semiconductor devices) is formed on the upper surface of the pseudo wafer. The second surfaces of the sample blocks are provided with the second LSI's respectively. Each sample block may be formed with a wiring pattern for electrically connecting the first and second LSI's thereon. Each sample block can be used as a semiconductor chip. The scribing procedure or the dicing procedure tends to generate distortions in the resultant sample blocks which might cause failures of LSI's. The rearrangement of the sample blocks into the pseudo wafer is troublesome.
U.S. Pat. No. 5,955,776 corresponding to Japanese patent application publication number 2001-501779 discloses a spherical shaped semiconductor integrated circuit called a ball. Initially, a crystal formation process forms a single spherical crystal. Upon the formation of the spherical crystal, a fabrication process constructs a circuit onto the spherical crystal to form a ball. A plurality of balls are made. Then, a clustering process connects the balls with each other and other devices such as printed circuit boards. The fabrication process and the clustering process tend to have complicated steps.
Japanese patent application publication number 10-256476 discloses a columnar semiconductor device which is fabricated as follows. A reticle has a circuit pattern. A light beam is applied to a slit-like region of the circuit pattern on the reticle before being focused on the cylindrical surface of a silicon column. This step transfers a part of the circuit pattern onto the cylindrical surface of the silicon column. As the beam-applied slit-like region is moved across the circuit pattern, the silicon column is rotated about its axis. Therefore, the whole of the circuit pattern is transferred onto the cylindrical surface of the silicon column to form a columnar semiconductor device. Position detection marks are provided on the silicon column. A position detecting system uses the position detection marks in sensing a positional error of the silicon column. The positional error of the silicon column is corrected before the circuit pattern is transferred onto the cylindrical surface thereof. Plural semiconductor devices are juxtaposed while being connected with each other and being connected with a power supply line by bumps.
Japanese patent application publication number 9-205177 discloses a semiconductor device having a hexahedral package. The top, bottom, and sides of the package are formed by printed wiring boards. Semiconductor chips are mounted on the inner surfaces of the printed wiring boards which form the sides of the package. Connection terminals are provided on the outer surfaces of the printed wiring boards which form the top, bottom, and sides of the package. The connection terminals are electrically connected with the semiconductor chips. Each of the connection terminals has a male connector and a female connector integral with each other. A cylindrical pipe for conducting cooled air extends through the package. Specifically, the cylindrical pipe extends between the top and the bottom of the package. Plural semiconductor devices are two-dimensionally or three-dimensionally arranged while the connection terminals thereon are fitted into each other. In this case, the semiconductor devices compose a large electronic circuit.
Japanese patent application publication number 8-298304 discloses a temperature-controllable block for carrying chips. The block has a hexahedral hollow body. Connectors for receiving chips are provided on the outer surfaces of the top, bottom and sides of the body. Each of the connectors has a recess for receiving a chip, and wiring metal members. The chips received by the connectors can be electrically connected with each other by wires. An inlet pipe and an outlet pipe in communication with the interior space of the body are supported by the body walls. Temperature controlling fluid such as air, oil, or water can be introduced into the interior of the body via the inlet pipe. The temperature controlling fluid can be moved from the interior of the body via the outlet pipe.
U.S. Pat. No. 4,801,992 discloses a modular circuit including individual planar integrated circuits which are connected together and to an interconnect chip. The modular circuit is fabricated as follows. Individual integrated circuits are formed on a wafer. Then, metal lines are formed on the wafer. Thereafter, individual circuit chips are formed by cutting the wafer. Four individual circuit chips are assembled together over a hollow core. The core may provide both a mounting surface for the individual circuit chips and a heat transfer device for dissipating heat from the individual circuit chips. The individual circuit chips may be electrically connected by related metal lines. The four integrated circuit chips composing the hollow core are attached to a fifth side of a cube which comprises a bump chip with various interconnect lines to the other four integrated circuit chips. The integrated circuit cube is bump mounted to a laminated area array tape which is in turn mounted to a lead line package.
SUMMARY OF THE INVENTION
It is a first object of this invention to provide an improved semiconductor device arrangement.
It is a second object of this invention to provide a method of fabricating an improved semiconductor device arrangement.
A first aspect of this invention provides a semiconductor device arrangement comprising a plurality of three-dimensional semiconductor units, wherein each of the three-dimensional semiconductor uni
Morishita Toshiyuki
Nagaya Masatake
Denso Corporation
Menz Douglas
Nguyen Van Thu
Posz & Bethards, PLC
LandOfFree
Semiconductor device arrangement and method of fabricating... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device arrangement and method of fabricating..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device arrangement and method of fabricating... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3218013